OV - exec - Loop 920

0x450698 ADD	X17, X15, X16

0x45069c LDR	D16, [X15]    [9]

0x4506a0 ORR	X18, XZR, X14

0x4506a4 ADD	X25, X17, X16

0x4506a8 ADD	X26, X25, X16

0x4506ac LDR	D7, [X15, X16]    [11]

0x4506b0 ADD	X27, X26, X16

0x4506b4 ADD	X28, X27, X16

0x4506b8 LDR	D8, [X17, X16]    [8]

0x4506bc ADD	X30, X28, X16

0x4506c0 LDR	D17, [X28, X16]    [2]

0x4506c4 ADD	X15, X30, X16,LSL #1

0x4506c8 STR	D16, [X18], #8    [10]

0x4506cc LDR	D18, [X30, X16]    [1]

0x4506d0 STR	D7, [X14, #8]    [4]

0x4506d4 LDR	D19, [X27, X16]    [3]

0x4506d8 STR	D8, [X18, #8]    [10]

0x4506dc LDR	D20, [X26, X16]    [7]

0x4506e0 LDR	D21, [X25, X16]    [5]

0x4506e4 STP	D17, D18, [X14, #48]    [4]

0x4506e8 STP	D20, D19, [X14, #32]    [4]

0x4506ec ADD	X14, X14, #64

0x4506f0 STUR	D21, [X14, #472]    [6]

0x4506f4 CMP	X4, X14

0x4506f8 B.NE	450698

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 210 - 211

--------------------------------------------------------------------------------

210:     for (size_t j = 0; j < m; ++j)

211:       B[i * ldb + j] = A[j * lda + i];

Coverage (%)	Name	Source Location	Module
►54.55+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►45.45+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::invertPsiM(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&)
Source	inner_product.hpp:210-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.89
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::invertPsiM(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&)
Source	inner_product.hpp:210-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.89
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::invertPsiM(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&)
Source file and lines	inner_product.hpp:210-211
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:210-211.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.89 cycles (3.70x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	3.13
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 450698

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X17, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X18, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D7, [X15, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X27, X26, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X27, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D8, [X17, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X28, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D17, [X28, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X15, X30, X16,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D16, [X18], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D18, [X30, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X14, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D19, [X27, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D8, [X18, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D20, [X26, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X25, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D17, D18, [X14, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D20, D19, [X14, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR D21, [X14, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 450698 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::invertPsiM(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&)
Source file and lines	inner_product.hpp:210-211
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:210-211.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.89 cycles (3.70x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	3.00	3.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	3.13
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

all	14%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 450698

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X17, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X18, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D7, [X15, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X27, X26, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X27, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D8, [X17, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X28, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D17, [X28, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X15, X30, X16,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D16, [X18], #8	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D18, [X30, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X14, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D19, [X27, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D8, [X18, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D20, [X26, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X25, X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D17, D18, [X14, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D20, D19, [X14, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR D21, [X14, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 450698 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code