OV - exec - Loop 910

0x44fef4 ADD	X18, X0, #168

0x44fef8 STP	XZR, XZR, [X0]    [1]

0x44fefc STP	XZR, XZR, [X0, #16]    [1]

0x44ff00 STP	XZR, XZR, [X0, #32]    [1]

0x44ff04 STP	XZR, XZR, [X0, #48]    [1]

0x44ff08 STP	XZR, XZR, [X0, #64]    [1]

0x44ff0c STP	XZR, XZR, [X0, #80]    [1]

0x44ff10 STP	XZR, XZR, [X0, #96]    [1]

0x44ff14 STP	XZR, XZR, [X0, #112]    [1]

0x44ff18 STP	XZR, XZR, [X0, #128]    [1]

0x44ff1c STP	XZR, XZR, [X0, #144]    [1]

0x44ff20 STP	XZR, XZR, [X0, #160]    [1]

0x44ff24 ADD	X0, X0, #192

0x44ff28 STP	XZR, XZR, [X18, #8]    [2]

0x44ff2c CMP	X12, X0

0x44ff30 B.NE	44fef4

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/usr/include/c++/11/bits/stl_algobase.h: 911 - 911

--------------------------------------------------------------------------------

911:       for (; __first != __last; ++__first)

Coverage (%)	Name	Source Location	Module
►60.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:83	exec
○	main._omp_fn.0	miniqmc.cpp:389	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►40.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:84	exec
○	main._omp_fn.0	miniqmc.cpp:389	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks	P10, P11, P13, P14,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	OperatorTags.h:183-183,stl_algobase.h:911-911
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks	P10, P11, P13, P14,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	OperatorTags.h:183-183,stl_algobase.h:911-911
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:911-911
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/usr/include/c++/11/bits/stl_algobase.h:911

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	0.00	6.00	6.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	0.00	6.00	6.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

66% of peak store performance is reached (32.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fef4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
ADD X18, X0, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP XZR, XZR, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #112]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #128]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #160]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X0, X0, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP XZR, XZR, [X18, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 44fef4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:911-911
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/usr/include/c++/11/bits/stl_algobase.h:911

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	0.00	6.00	6.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	0.00	6.00	6.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

66% of peak store performance is reached (32.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fef4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
ADD X18, X0, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP XZR, XZR, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #112]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #128]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STP XZR, XZR, [X0, #160]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X0, X0, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP XZR, XZR, [X18, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 44fef4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code