OV - exec - Loop 893

0x44d87c LDR	D24, [X6, X15,LSL #3]    [5]

0x44d880 ADD	X5, X15, #1

0x44d884 ADD	X9, X15, #2

0x44d888 ADD	X0, X15, #3

0x44d88c ADD	X15, X15, #4

0x44d890 LDP	D28, D26, [X18, #8]    [7]

0x44d894 ADD	X18, X18, #96

0x44d898 LDUR	D30, [X18, #448]    [1]

0x44d89c LDUR	D4, [X18, #456]    [1]

0x44d8a0 LDR	D25, [X6, X5,LSL #3]    [4]

0x44d8a4 FMADD	D7, D28, D24, D1

0x44d8a8 FMADD	D6, D24, D26, D0

0x44d8ac LDUR	D3, [X18, #416]    [1]

0x44d8b0 LDUR	D31, [X18, #472]    [1]

0x44d8b4 LDUR	D19, [X18, #480]    [1]

0x44d8b8 FMADD	D16, D30, D25, D7

0x44d8bc FMADD	D20, D25, D4, D6

0x44d8c0 LDR	D27, [X6, X9,LSL #3]    [6]

0x44d8c4 FMADD	D23, D3, D24, D2

0x44d8c8 LDUR	D5, [X18, #496]    [1]

0x44d8cc LDUR	D17, [X18, #504]    [1]

0x44d8d0 LDR	D21, [X6, X0,LSL #3]    [2]

0x44d8d4 FMADD	D18, D31, D27, D16

0x44d8d8 FMADD	D22, D27, D19, D20

0x44d8dc LDUR	D2, [X18, #440]    [1]

0x44d8e0 LDUR	D24, [X18, #464]    [1]

0x44d8e4 FMADD	D1, D5, D21, D18

0x44d8e8 FMADD	D0, D21, D17, D22

0x44d8ec LDUR	D28, [X18, #488]    [1]

0x44d8f0 FMADD	D25, D2, D25, D23

0x44d8f4 FMADD	D27, D24, D27, D25

0x44d8f8 STP	D1, D0, [SP, #296]    [3]

0x44d8fc FMADD	D2, D28, D21, D27

0x44d900 CMP	W16, W15

0x44d904 B.GT	44d87c

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 154 - 154

--------------------------------------------------------------------------------

154:   for (int i = 0; i < n; i++)

Coverage (%)	Name	Source Location	Module
►25.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►18.75+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►12.50+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►6.25+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►6.25+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►6.25+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	OperatorTags.h:63-63,OperatorTags.h:94-94,inner_product.hpp:154-154
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.11
Front-end cycles	4.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	5.50
P10 cycles	5.17
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.50
Vectorization ratio load	6.67
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	26.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	OperatorTags.h:63-63,OperatorTags.h:94-94,inner_product.hpp:154-154
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.11
Front-end cycles	4.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	5.50
P10 cycles	5.17
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.50
Vectorization ratio load	6.67
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	26.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.11 cycles (3.78x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	35
loop length	140
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	5.50	5.17	5.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	5.50	5.17	5.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.38
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	12%
load	6%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44d87c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D24, [X6, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X5, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D28, D26, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D30, [X18, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D4, [X18, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X6, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D28, D24, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D6, D24, D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D3, [X18, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D31, [X18, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D19, [X18, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D30, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D20, D25, D4, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D27, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D3, D24, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D5, [X18, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D17, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D18, D31, D27, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D22, D27, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D2, [X18, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D24, [X18, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D5, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D0, D21, D17, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D28, [X18, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D25, D2, D25, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D24, D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D1, D0, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D2, D28, D21, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 44d87c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.11 cycles (3.78x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	35
loop length	140
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	5.50	5.17	5.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	5.50	5.17	5.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.38
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	12%
load	6%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44d87c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D24, [X6, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X5, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D28, D26, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D30, [X18, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D4, [X18, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X6, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D28, D24, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D6, D24, D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D3, [X18, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D31, [X18, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D19, [X18, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D30, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D20, D25, D4, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D27, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D3, D24, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D5, [X18, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D17, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D18, D31, D27, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D22, D27, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D2, [X18, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D24, [X18, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D5, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D0, D21, D17, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D28, [X18, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D25, D2, D25, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D24, D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D1, D0, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D2, D28, D21, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 44d87c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code