OV - exec - Loop 889

0x44d070 LDR	X0, [X19, #1088]    [6]

0x44d074 BL	47a180

0x44d078 ADRP	X2,

0x44d07c FMOV	D31, #1.0000000

0x44d080 LDR	X25, [X2, #4016]    [4]

0x44d084 STR	D31, [X19, #1080]    [6]

0x44d088 LDR	X2, [SP, #408]    [2]

0x44d08c LDR	X1, [X25]    [3]

0x44d090 SUBS	X2, X2, X1

0x44d094 MOVZ	X1, #0

0x44d098 B.NE	44d57c

0x44d09c LDP	X29, X30, [SP, #48]    [2]

0x44d0a0 LDP	X19, X20, [SP, #64]    [2]

0x44d0a4 LDP	X21, X22, [SP, #80]    [2]

0x44d0a8 LDP	X23, X24, [SP, #96]    [2]

0x44d0ac LDP	X25, X26, [SP, #112]    [2]

0x44d0b0 LDP	X27, X28, [SP, #128]    [2]

0x44d0b4 LDP	D8, D9, [SP, #144]    [2]

0x44d0b8 ADD	SP, SP, #416

0x44d0bc RET

0x44d0c0 LDR	X26, [SP, #200]    [1]

0x44d0c4 MOVZ	W3, #24

0x44d0c8 LDR	X7, [X19, #280]    [5]

0x44d0cc LDR	W1, [X19, #1152]    [5]

0x44d0d0 LDR	X4, [X19, #320]    [5]

0x44d0d4 MADD	X5, X26, X7, XZR

0x44d0d8 SMADDL	X2, W1, W3, XZR

0x44d0dc LDR	X1, [X19, #464]    [5]

0x44d0e0 ADD	X30, X5, X5,LSL #1

0x44d0e4 ADD	X0, X4, X30,LSL #3

0x44d0e8 BL	4039b0

0x44d0ec LDR	X8, [X19, #344]    [5]

0x44d0f0 LDRSW	X11, [X19, #1152]    [5]

0x44d0f4 LDR	X28, [X19, #384]    [5]

0x44d0f8 MADD	X13, X26, X8, XZR

0x44d0fc LDR	X1, [X19, #504]    [5]

0x44d100 UBFM	X2, X11, #61, #60

0x44d104 ADD	X0, X28, X13,LSL #3

0x44d108 BL	4039b0

0x44d10c B	44d070

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 137 - 139

--------------------------------------------------------------------------------

137:   UpdateTimer->stop();

138:   curRatio = 1.0;

139: }

/usr/include/aarch64-linux-gnu/bits/string_fortified.h: 34 - 34

--------------------------------------------------------------------------------

34:   return __builtin___memcpy_chk (__dest, __src, __len, __bos0 (__dest));

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 52 - 53

--------------------------------------------------------------------------------

52:   memcpy(target, source, sizeof(T) * n);

53: }

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::acc[...]	stl_vector.h:918	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	3.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	DiracDeterminantRef.cpp:137-139,string_fortified.h:34-34,OhmmsMatrix.h:217-217,inner_product.hpp:52-53
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	1.04
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	7.17
P10 cycles	6.83
P11 cycles	7.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.14
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	16.67
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.08
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	3.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	DiracDeterminantRef.cpp:137-139,string_fortified.h:34-34,OhmmsMatrix.h:217-217,inner_product.hpp:52-53
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	1.04
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	7.17
P10 cycles	6.83
P11 cycles	7.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.14
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	16.67
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.08
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:52-53
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:137-139
/usr/include/aarch64-linux-gnu/bits/string_fortified.h:34
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:52-53

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.17 to 1.83 cycles (3.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.17 to 1.04 cycles (6.88x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.17 to 1.50 cycles (4.78x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.75	3.75	3.75	3.75	0.50	0.50	0.50	0.50	7.17	6.83	7.00	0.00	0.00
cycles	3.00	3.00	3.75	3.75	3.75	3.75	0.50	0.50	0.50	0.50	7.17	6.83	7.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Overall L1	7.17

Vectorization ratios

all	16%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

30% of peak load performance is reached (29.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44d0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X2, <4c1078>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X25, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X19, #1080]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X2, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 44d57c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X19, X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X23, X24, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X25, X26, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X27, X28, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D8, D9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD SP, SP, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ W3, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X7, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W1, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X5, X26, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
SMADDL X2, W1, W3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X5, X5,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X4, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDRSW X11, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X28, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X13, X26, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X2, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X28, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44d070 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:52-53
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:137-139
/usr/include/aarch64-linux-gnu/bits/string_fortified.h:34
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:52-53

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.17 to 1.83 cycles (3.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.17 to 1.04 cycles (6.88x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.17 to 1.50 cycles (4.78x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.75	3.75	3.75	3.75	0.50	0.50	0.50	0.50	7.17	6.83	7.00	0.00	0.00
cycles	3.00	3.00	3.75	3.75	3.75	3.75	0.50	0.50	0.50	0.50	7.17	6.83	7.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Overall L1	7.17

Vectorization ratios

all	16%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

30% of peak load performance is reached (29.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44d0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X2, <4c1078>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X25, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X19, #1080]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X2, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 44d57c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X19, X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X23, X24, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X25, X26, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X27, X28, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D8, D9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD SP, SP, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ W3, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X7, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W1, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X5, X26, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
SMADDL X2, W1, W3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X5, X5,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X4, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDRSW X11, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X28, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X13, X26, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X2, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X28, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44d070 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code