OV - exec - Loop 814

	Loop Id: 814	Module: exec	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.22%

0x444b28 LDR	D25, [X8, X0,LSL #3]    [29]

0x444b2c ADD	X3, X0, #1

0x444b30 ADD	X4, X0, #2

0x444b34 ADD	X2, X0, #3

0x444b38 ADD	X10, X1, #72

0x444b3c STR	D25, [X7, X0,LSL #3]    [3]

0x444b40 LDR	D26, [X5, X0,LSL #3]    [20]

0x444b44 LDR	D27, [X12, X0,LSL #3]    [1]

0x444b48 LDR	D10, [X11, X0,LSL #3]    [22]

0x444b4c STP	D26, D27, [X1]    [24]

0x444b50 STR	D10, [X1, #16]    [24]

0x444b54 LDR	D9, [X9, X0,LSL #3]    [7]

0x444b58 STR	D9, [X6, X0,LSL #3]    [14]

0x444b5c ADD	X0, X0, #4

0x444b60 LDR	D28, [X8, X3,LSL #3]    [10]

0x444b64 STR	D28, [X7, X3,LSL #3]    [12]

0x444b68 LDR	D29, [X5, X3,LSL #3]    [28]

0x444b6c LDR	D30, [X12, X3,LSL #3]    [18]

0x444b70 LDR	D31, [X11, X3,LSL #3]    [21]

0x444b74 STP	D29, D30, [X1, #24]    [24]

0x444b78 STR	D31, [X1, #40]    [24]

0x444b7c LDR	D6, [X9, X3,LSL #3]    [27]

0x444b80 STR	D6, [X6, X3,LSL #3]    [5]

0x444b84 LDR	D0, [X8, X4,LSL #3]    [23]

0x444b88 STR	D0, [X7, X4,LSL #3]    [8]

0x444b8c LDR	D8, [X5, X4,LSL #3]    [25]

0x444b90 LDR	D4, [X12, X4,LSL #3]    [17]

0x444b94 LDR	D3, [X11, X4,LSL #3]    [31]

0x444b98 STP	D8, D4, [X1, #48]    [24]

0x444b9c ADD	X1, X1, #96

0x444ba0 STUR	D3, [X1, #480]    [9]

0x444ba4 LDR	D5, [X9, X4,LSL #3]    [6]

0x444ba8 STR	D5, [X6, X4,LSL #3]    [16]

0x444bac LDR	D17, [X8, X2,LSL #3]    [13]

0x444bb0 STR	D17, [X7, X2,LSL #3]    [2]

0x444bb4 LDR	D2, [X5, X2,LSL #3]    [30]

0x444bb8 LDR	D1, [X12, X2,LSL #3]    [15]

0x444bbc LDR	D16, [X11, X2,LSL #3]    [19]

0x444bc0 STUR	D2, [X1, #488]    [9]

0x444bc4 STP	D1, D16, [X10, #8]    [26]

0x444bc8 LDR	D7, [X9, X2,LSL #3]    [11]

0x444bcc STR	D7, [X6, X2,LSL #3]    [4]

0x444bd0 CMP	X2, X19

0x444bd4 B.NE	444b28

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 146 - 146

--------------------------------------------------------------------------------

146:       X[i] = base[i * offset];

Coverage (%)	Name	Source Location	Module
►17.86+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►10.71+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►7.14+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►7.14+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►7.14+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►3.57+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►3.57+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:202	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	OperatorTags.h:183-183,einspline_spo_ref.hpp:223-227,TinyVector.h:146-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.33
Front-end cycles	5.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	27.78
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source	OperatorTags.h:183-183,einspline_spo_ref.hpp:223-227,TinyVector.h:146-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.33
Front-end cycles	5.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	27.78
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	31.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:146

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 3.33 cycles (3.60x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 444b28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR D25, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X1, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D25, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D26, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D10, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D26, D27, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D10, [X1, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D9, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D9, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D28, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D28, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D29, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D30, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D31, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D29, D30, [X1, #24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D31, [X1, #40]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D8, [X5, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D8, D4, [X1, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X1, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR D3, [X1, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D17, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D2, [X1, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D1, D16, [X10, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D7, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 444b28 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:146

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	8.00	8.00	0.00	0.00	12.00	12.00	12.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 444b28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
LDR D25, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X1, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D25, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D26, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D10, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D26, D27, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D10, [X1, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D9, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D9, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D28, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D28, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D29, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D30, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D31, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D29, D30, [X1, #24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D31, [X1, #40]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D8, [X5, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STP D8, D4, [X1, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X1, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR D3, [X1, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D17, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D17, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D2, [X1, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STP D1, D16, [X10, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D7, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 444b28 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code