OV - exec - Loop 811

0x444274 ADD	X9, X13, X7

0x444278 FMUL	D20, D9, D17

0x44427c FMUL	D3, D11, D5

0x444280 ADD	X8, X13, X9

0x444284 FMUL	D1, D10, D5

0x444288 FMUL	D4, D9, D5

0x44428c FMUL	D6, D10, D18

0x444290 FMUL	D19, D9, D18

0x444294 ADD	X10, X13, X8

0x444298 CMP	W15, #0

0x44429c B.LE	444394

0x4442a0 ORR	W6, WZR, W25

0x4442a4 MOVZ	X0, #0

0x4442a8 DUP	Z16.D, Z6.D[0]

0x4442ac DUP	Z17.D, Z3.D[0]

0x4442b0 DUP	Z6.D, Z1.D[0]

0x4442b4 DUP	Z7.D, Z20.D[0]

0x4442b8 DUP	Z5.D, Z19.D[0]

0x4442bc DUP	Z4.D, Z4.D[0]

0x4442c0 ORR	P6.B, P8/Z, P8.B, P8.B

  (812) 0x4442c4 LD1D	{Z20.D}, P6/Z, [X10, X0,LSL #3]

  (812) 0x4442c8 LD1D	{Z1.D}, P6/Z, [X8, X0,LSL #3]

  (812) 0x4442cc FMUL	Z19.D, Z27.D, Z20.D

  (812) 0x4442d0 FMLA	Z19.D, P5/M, Z22.D, Z1.D

  (812) 0x4442d4 LD1D	{Z18.D}, P6/Z, [X20, X0,LSL #3]

  (812) 0x4442d8 LD1D	{Z2.D}, P6/Z, [X9, X0,LSL #3]

  (812) 0x4442dc LD1D	{Z3.D}, P6/Z, [X7, X0,LSL #3]

  (812) 0x4442e0 FMUL	Z0.D, Z8.D, Z2.D

  (812) 0x4442e4 FMLA	Z0.D, P5/M, Z25.D, Z3.D

  (812) 0x4442e8 FADD	Z0.D, Z0.D, Z19.D

  (812) 0x4442ec FMUL	Z19.D, Z31.D, Z2.D

  (812) 0x4442f0 FMLA	Z18.D, P5/M, Z17.D, Z0.D

  (812) 0x4442f4 FMLA	Z19.D, P5/M, Z26.D, Z3.D

  (812) 0x4442f8 FMUL	Z2.D, Z28.D, Z2.D

  (812) 0x4442fc FMAD	Z3.D, P5/M, Z29.D, Z2.D

  (812) 0x444300 FMUL	Z2.D, Z23.D, Z20.D

  (812) 0x444304 FMUL	Z20.D, Z21.D, Z20.D

  (812) 0x444308 FMLA	Z2.D, P5/M, Z30.D, Z1.D

  (812) 0x44430c FMAD	Z1.D, P5/M, Z24.D, Z20.D

  (812) 0x444310 FADD	Z2.D, Z19.D, Z2.D

  (812) 0x444314 FADD	Z1.D, Z3.D, Z1.D

  (812) 0x444318 LD1D	{Z19.D}, P6/Z, [X19, X0,LSL #3]

  (812) 0x44431c FMLA	Z19.D, P5/M, Z6.D, Z0.D

  (812) 0x444320 ST1D	{Z18.D}, P6, [X20, X0,LSL #3]

  (812) 0x444324 LD1D	{Z3.D}, P6/Z, [X3, X0,LSL #3]

  (812) 0x444328 FMLA	Z3.D, P5/M, Z16.D, Z0.D

  (812) 0x44432c ST1D	{Z19.D}, P6, [X19, X0,LSL #3]

  (812) 0x444330 LD1D	{Z18.D}, P6/Z, [X21, X0,LSL #3]

  (812) 0x444334 FMLA	Z18.D, P5/M, Z0.D, Z5.D

  (812) 0x444338 ST1D	{Z3.D}, P6, [X3, X0,LSL #3]

  (812) 0x44433c LD1D	{Z20.D}, P6/Z, [X5, X0,LSL #3]

  (812) 0x444340 FMLA	Z20.D, P5/M, Z6.D, Z2.D

  (812) 0x444344 ST1D	{Z18.D}, P6, [X21, X0,LSL #3]

  (812) 0x444348 LD1D	{Z19.D}, P6/Z, [X22, X0,LSL #3]

  (812) 0x44434c FMLA	Z19.D, P5/M, Z2.D, Z4.D

  (812) 0x444350 ST1D	{Z20.D}, P6, [X5, X0,LSL #3]

  (812) 0x444354 LD1D	{Z3.D}, P6/Z, [X1, X0,LSL #3]

  (812) 0x444358 FMLA	Z3.D, P5/M, Z7.D, Z0.D

  (812) 0x44435c ST1D	{Z3.D}, P6, [X1, X0,LSL #3]

  (812) 0x444360 LD1D	{Z18.D}, P6/Z, [X2, X0,LSL #3]

  (812) 0x444364 FMAD	Z2.D, P5/M, Z5.D, Z18.D

  (812) 0x444368 ST1D	{Z19.D}, P6, [X22, X0,LSL #3]

  (812) 0x44436c ST1D	{Z2.D}, P6, [X2, X0,LSL #3]

  (812) 0x444370 LD1D	{Z2.D}, P6/Z, [X24, X0,LSL #3]

  (812) 0x444374 FMAD	Z1.D, P5/M, Z4.D, Z2.D

  (812) 0x444378 ST1D	{Z1.D}, P6, [X24, X0,LSL #3]

  (812) 0x44437c LD1D	{Z1.D}, P6/Z, [X23, X0,LSL #3]

  (812) 0x444380 FMAD	Z0.D, P5/M, Z4.D, Z1.D

  (812) 0x444384 ST1D	{Z0.D}, P6, [X23, X0,LSL #3]

  (812) 0x444388 ADD	X0, X0, X11

  (812) 0x44438c WHILELO	P6.D, W0, W6

  (812) 0x444390 B.NE	4442c4

0x444394 ADD	X7, X7, X14

0x444398 CMP	X12, #24

0x44439c B.EQ	4444e0

0x4443a0 ADD	X9, X12, X18

0x4443a4 ADD	X8, X12, X17

0x4443a8 ADD	X10, X12, X16

0x4443ac ADD	X12, X12, #8

0x4443b0 LDR	D18, [X8, #8]

0x4443b4 LDR	D17, [X10, #8]

0x4443b8 LDR	D5, [X9, #8]

0x4443bc B	444274

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 234 - 270

--------------------------------------------------------------------------------

234:     for (int j = 0; j < 4; j++)

[...]

241:       const T pre20 = d2a[i] * b[j];

242:       const T pre10 = da[i] * b[j];

243:       const T pre00 = a[i] * b[j];

244:       const T pre11 = da[i] * db[j];

245:       const T pre01 = a[i] * db[j];

246:       const T pre02 = a[i] * d2b[j];

247:

248:       const int iSplitPoint = num_splines;

249: #pragma omp simd aligned(coefs, coefszs, coefs2zs, coefs3zs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_)

250:       for (int n = 0; n < iSplitPoint; n++)

251:       {

252:         T coefsv    = coefs[n];

253:         T coefsvzs  = coefszs[n];

254:         T coefsv2zs = coefs2zs[n];

255:         T coefsv3zs = coefs3zs[n];

256:

257:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

258:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

259:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

260:

261:         hxx[n] += pre20 * sum0;

262:         hxy[n] += pre11 * sum0;

263:         hxz[n] += pre10 * sum1;

264:         hyy[n] += pre02 * sum0;

265:         hyz[n] += pre01 * sum1;

266:         hzz[n] += pre00 * sum2;

267:         gx[n] += pre10 * sum0;

268:         gy[n] += pre01 * sum0;

269:         gz[n] += pre00 * sum1;

270:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.66
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:234-234,MultiBsplineRef.hpp:241-246,MultiBsplineRef.hpp:249-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.31
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.31
CQA cycles if fully vectorized	1.75
Front-end cycles	3.31
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	2.88
P2 cycles	2.88
P3 cycles	2.88
P4 cycles	2.88
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.50
Nb uops	26.50
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.81
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.46
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	31.82
Vector-efficiency ratio all	37.71
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	40.63

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.26
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:234-234,MultiBsplineRef.hpp:241-246,MultiBsplineRef.hpp:249-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	3.08
Front-end cycles	3.88
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.55
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.19
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	46.67
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	63.64
Vector-efficiency ratio all	52.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Metric	Value
CQA speedup if no scalar integer	2.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:234-234,MultiBsplineRef.hpp:241-246,MultiBsplineRef.hpp:249-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.42
Front-end cycles	2.75
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.18
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.73
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:234-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-246,249.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.31 to 1.75 cycles (1.89x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	26.50
loop length	106
nb stack references	0

Front-end

front end

3.31 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.88	2.88	2.88	2.88	2.25	2.25	2.25	2.25	1.00	1.00	1.00	0.00	0.00
cycles	1.50	1.50	2.88	2.88	2.88	2.88	2.25	2.25	2.25	2.25	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.31
Data deps.	1.00
Overall L1	3.31

Vectorization ratios

all	23%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.31 cycles. At this rate:

7% of peak load performance is reached (7.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:234-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-246,249.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.88 to 3.00 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 3.08 cycles (1.26x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.25	3.25	3.25	3.25	3.00	3.00	3.00	3.00	1.00	1.00	1.00	0.00	0.00
cycles	1.50	1.50	3.25	3.25	3.25	3.25	3.00	3.00	3.00	3.00	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.88
Data deps.	1.00
Overall L1	3.88

Vectorization ratios

all	46%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	63%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

6% of peak load performance is reached (6.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 444274

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X9, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D20, D9, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D3, D11, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X8, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D1, D10, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D4, D9, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D6, D10, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D19, D9, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X10, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 444394 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W6, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DUP Z16.D, Z6.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z17.D, Z3.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z6.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z7.D, Z20.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z5.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ORR P6.B, P8/Z, P8.B, P8.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
ADD X7, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4444e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D5, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 444274 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:234-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:234,241-246,249.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 1.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.42 cycles (6.52x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	1.50	1.50	1.50	1.50	1.00	1.00	1.00	0.00	0.00
cycles	1.50	1.50	2.50	2.50	2.50	2.50	1.50	1.50	1.50	1.50	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.75
Data deps.	1.00
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

9% of peak load performance is reached (8.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 444274

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X9, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D20, D9, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D3, D11, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X8, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D1, D10, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D4, D9, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D6, D10, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D19, D9, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X10, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 444394 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X7, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4444e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D5, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 444274 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code