OV - exec - Loop 804

0x4434ac LDR	X17, [X9, X18,LSL #3]    [1]

0x4434b0 ADD	X18, X18, #1

0x4434b4 HINT	#0

0x4434b8 HINT	#0

0x4434bc HINT	#0

0x4434c0 UBFM	X16, X17, #11, #42

0x4434c4 EOR	X12, X16, X17

0x4434c8 AND	X14, X7, X12,LSL #7

0x4434cc EOR	X30, X12, X14

0x4434d0 AND	X13, X6, X30,LSL #15

0x4434d4 EOR	X17, X30, X13

0x4434d8 EOR	X0, X17, X17,LSR #18

0x4434dc UCVTF	D0, X0

0x4434e0 FMADD	D1, D2, D0, D1

0x4434e4 FMUL	D2, D2, D28

0x4434e8 CMP	W5, #1

0x4434ec B.EQ	44347c

0x4434f0 MOVZ	W5, #1

0x4434f4 CMP	X18, #623

0x4434f8 B.LS	4434ac

/usr/include/c++/11/bits/random.tcc: 455 - 3363

--------------------------------------------------------------------------------

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3360:       for (size_t __k = __m; __k != 0; --__k)

3361: 	{

3362: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3363: 	  __tmp *= __r;

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::build_SPOSet(bool[...]	OperatorTags.h:183	exec
○	main	unique_ptr.h:371	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::set(int, int, int, int, int, bool)
Source	random.tcc:455-463,random.tcc:3360-3363
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.59
Front-end cycles	2.13
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.22
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.22

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::set(int, int, int, int, int, bool)
Source	random.tcc:455-463,random.tcc:3360-3363
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.59
Front-end cycles	2.13
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.22
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.22

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::set(int, int, int, int, int, bool)
Source file and lines	random.tcc:455-3363
Module	exec

The loop is defined in /usr/include/c++/11/bits/random.tcc:455-463,3360-3363.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.59 cycles (5.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	0.33	0.33	0.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4434c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
UBFM X16, X17, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X12, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X14, X7, X12,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X30, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X13, X6, X30,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X17, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X0, X17, X17,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UCVTF D0, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
FMADD D1, D2, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D2, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44347c <_ZN16miniqmcreference17einspline_spo_refIdE3setEiiiiib+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #623	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 4434ac <_ZN16miniqmcreference17einspline_spo_refIdE3setEiiiiib+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::set(int, int, int, int, int, bool)
Source file and lines	random.tcc:455-3363
Module	exec

The loop is defined in /usr/include/c++/11/bits/random.tcc:455-463,3360-3363.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.59 cycles (5.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	0.33	0.33	0.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4434c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
UBFM X16, X17, #11, #42	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X12, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X14, X7, X12,LSL #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X30, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X13, X6, X30,LSL #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X17, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X0, X17, X17,LSR #18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UCVTF D0, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
FMADD D1, D2, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D2, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44347c <_ZN16miniqmcreference17einspline_spo_refIdE3setEiiiiib+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #623	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 4434ac <_ZN16miniqmcreference17einspline_spo_refIdE3setEiiiiib+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code