OV - exec - Loop 730

	Loop Id: 730	Module: exec	Source: BsplineFunctor.h:246-260	Coverage: 0.02%

0x43c340 LDR	D3, [X5, X9,LSL #3]    [3]

0x43c344 ADD	X10, X9, #1

0x43c348 ADD	X9, X9, #2

0x43c34c LDR	D1, [X5, X10,LSL #3]    [1]

0x43c350 FMUL	D10, D31, D3

0x43c354 FMUL	D5, D31, D1

0x43c358 FCVTZS	W11, D10

0x43c35c ADD	X12, X18, W11,SXTW #3

0x43c360 LDR	D6, [X12, #24]    [5]

0x43c364 FCVTZS	W13, D5

0x43c368 ADD	X14, X18, W13,SXTW #3

0x43c36c LDR	D1, [X14, #24]    [7]

0x43c370 SCVTF	D18, W11

0x43c374 LDR	D17, [X18, X11,SXTW #3]    [4]

0x43c378 LDR	D16, [X18, X13,SXTW #3]    [6]

0x43c37c FSUB	D2, D10, S18

0x43c380 SCVTF	D10, W13

0x43c384 LDP	D18, D4, [X14, #8]    [7]

0x43c388 FMUL	D9, D2, D2

0x43c38c FMADD	D7, D28, D2, D27

0x43c390 STP	D4, D1, [SP, #88]    [2]

0x43c394 FSUB	D1, D5, S10

0x43c398 FMADD	D4, D30, D2, D29

0x43c39c FMADD	D19, D9, D23, D7

0x43c3a0 FMUL	D15, D9, D2

0x43c3a4 FMUL	D7, D1, D1

0x43c3a8 FMADD	D5, D30, D1, D29

0x43c3ac FMADD	D8, D14, D15, D19

0x43c3b0 LDP	D19, D3, [X12, #8]    [5]

0x43c3b4 FMADD	D5, D7, D24, D5

0x43c3b8 FMUL	D10, D7, D1

0x43c3bc STP	D3, D6, [SP, #72]    [2]

0x43c3c0 FMADD	D6, D26, D2, D25

0x43c3c4 FMADD	D2, D21, D2, D20

0x43c3c8 FMADD	D3, D9, D24, D4

0x43c3cc FMADD	D2, D9, D12, D2

0x43c3d0 FMADD	D4, D9, D22, D6

0x43c3d4 FMADD	D9, D26, D1, D25

0x43c3d8 FMADD	D6, D13, D15, D4

0x43c3dc FMADD	D2, D11, D15, D2

0x43c3e0 FMADD	D4, D7, D22, D9

0x43c3e4 FMADD	D9, D13, D10, D4

0x43c3e8 LDR	D4, [SP, #104]    [2]

0x43c3ec FMADD	D15, D4, D15, D3

0x43c3f0 FMADD	D5, D4, D10, D5

0x43c3f4 FMADD	D3, D28, D1, D27

0x43c3f8 FMADD	D1, D21, D1, D20

0x43c3fc FMADD	D4, D7, D23, D3

0x43c400 FMUL	D19, D15, D19

0x43c404 FMUL	D18, D5, D18

0x43c408 LDR	D5, [SP, #72]    [2]

0x43c40c FMADD	D15, D14, D10, D4

0x43c410 LDR	D4, [SP, #88]    [2]

0x43c414 FMADD	D17, D17, D8, D19

0x43c418 FMADD	D8, D7, D12, D1

0x43c41c LDR	D7, [SP, #96]    [2]

0x43c420 FMADD	D16, D16, D15, D18

0x43c424 FMADD	D3, D5, D6, D17

0x43c428 LDR	D6, [SP, #80]    [2]

0x43c42c FMADD	D10, D11, D10, D8

0x43c430 FMADD	D9, D4, D9, D16

0x43c434 FMADD	D2, D6, D2, D3

0x43c438 FMADD	D19, D7, D10, D9

0x43c43c FADD	D0, D0, D2

0x43c440 FADD	D0, D0, D19

0x43c444 CMP	W8, W9

0x43c448 B.GT	43c340

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►50.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:219	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►50.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:219	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P6, P7, P8, P9,
Function	qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const
Source	BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	1.63
Front-end cycles	8.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.26
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.22
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.53
Vectorization ratio load	15.38
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	29.41
Vector-efficiency ratio load	28.85
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P6, P7, P8, P9,
Function	qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const
Source	BsplineFunctor.h:246-260
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	1.63
Front-end cycles	8.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.26
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.22
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.53
Vectorization ratio load	15.38
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	29.41
Vector-efficiency ratio load	28.85
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 5.00 cycles (2.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.50 to 1.62 cycles (7.08x speedup).

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

15% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences
SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

34: addition or subtraction (30 inside FMA instructions)
38: multiply (30 inside FMA instructions)

The binary loop is loading 120 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	67
loop length	268
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	2.00	2.00	11.50	11.50	11.50	11.50	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	2.00	2.00	11.50	11.50	11.50	11.50	5.00	5.00	5.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.38
Data deps.	4.00
Overall L1	11.50

Vectorization ratios

all	23%
load	15%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

10% of peak load performance is reached (10.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43c340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D3, [X5, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D10, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D5, D31, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCVTZS W11, D10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1
ADD X12, X18, W11,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDR D6, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCVTZS W13, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1
ADD X14, X18, W13,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDR D1, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D18, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
LDR D17, [X18, X11,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X18, X13,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D2, D10, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SCVTF D10, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
LDP D18, D4, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D9, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D7, D28, D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D4, D1, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D1, D5, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D4, D30, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D19, D9, D23, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D15, D9, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D7, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D5, D30, D1, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D14, D15, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D19, D3, [X12, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D7, D24, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D10, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP D3, D6, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D6, D26, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D21, D2, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D9, D24, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D9, D12, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D9, D22, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D26, D1, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D6, D13, D15, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D11, D15, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D7, D22, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D13, D10, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D15, D4, D15, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D5, D4, D10, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D28, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D1, D21, D1, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D7, D23, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D19, D15, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D5, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D15, D14, D10, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D17, D17, D8, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D7, D12, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D16, D15, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D5, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D6, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D10, D11, D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D4, D9, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D6, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D19, D7, D10, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 43c340 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const
Source file and lines	BsplineFunctor.h:246-260
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 5.00 cycles (2.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

15% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences
SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

34: addition or subtraction (30 inside FMA instructions)
38: multiply (30 inside FMA instructions)

The binary loop is loading 120 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	67
loop length	268
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	2.00	2.00	11.50	11.50	11.50	11.50	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	2.00	2.00	11.50	11.50	11.50	11.50	5.00	5.00	5.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.38
Data deps.	4.00
Overall L1	11.50

Vectorization ratios

all	23%
load	15%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

10% of peak load performance is reached (10.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43c340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D3, [X5, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D10, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D5, D31, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCVTZS W11, D10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1
ADD X12, X18, W11,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDR D6, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCVTZS W13, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1
ADD X14, X18, W13,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDR D1, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D18, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
LDR D17, [X18, X11,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X18, X13,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D2, D10, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SCVTF D10, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
LDP D18, D4, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D9, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D7, D28, D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D4, D1, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D1, D5, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D4, D30, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D19, D9, D23, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D15, D9, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D7, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D5, D30, D1, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D14, D15, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D19, D3, [X12, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D7, D24, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D10, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STP D3, D6, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D6, D26, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D21, D2, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D9, D24, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D9, D12, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D9, D22, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D26, D1, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D6, D13, D15, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D11, D15, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D7, D22, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D13, D10, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D15, D4, D15, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D5, D4, D10, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D28, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D1, D21, D1, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D4, D7, D23, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D19, D15, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D5, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D15, D14, D10, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D17, D17, D8, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D7, D12, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D16, D15, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D5, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D6, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D10, D11, D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D9, D4, D9, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D2, D6, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D19, D7, D10, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 43c340 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code