OV - exec - Loop 663

	Loop Id: 663	Module: exec	Source: BsplineFunctor.h:291-297	Coverage: 0.02%

0x437788 LDR	D16, [X18, X4,LSL #3]    [2]

0x43778c FCMPE	D0, D16

0x437790 B.LS	4377b0

0x437794 ADD	W12, W2, W4

0x437798 CMP	W12, W1

0x43779c B.EQ	4377b0

0x4377a0 SBFM	X13, X8, #0, #31

0x4377a4 ADD	W8, W8, #1

0x4377a8 STR	W4, [X16, X13,LSL #2]    [9]

0x4377ac STR	D16, [X15, X13,LSL #3]    [14]

0x4377b0 ADD	X4, X4, #1

0x4377b4 LDR	D17, [X18, X4,LSL #3]    [12]

0x4377b8 FCMPE	D0, D17

0x4377bc B.LS	4377dc

0x4377c0 ADD	W9, W2, W4

0x4377c4 CMP	W9, W1

0x4377c8 B.EQ	4377dc

0x4377cc SBFM	X11, X8, #0, #31

0x4377d0 ADD	W8, W8, #1

0x4377d4 STR	W4, [X16, X11,LSL #2]    [7]

0x4377d8 STR	D17, [X15, X11,LSL #3]    [11]

0x4377dc ADD	X10, X4, #1

0x4377e0 LDR	D18, [X18, X10,LSL #3]    [10]

0x4377e4 FCMPE	D0, D18

0x4377e8 B.LS	437808

0x4377ec ADD	W14, W2, W10

0x4377f0 CMP	W14, W1

0x4377f4 B.EQ	437808

0x4377f8 SBFM	X12, X8, #0, #31

0x4377fc ADD	W8, W8, #1

0x437800 STR	W10, [X16, X12,LSL #2]    [8]

0x437804 STR	D18, [X15, X12,LSL #3]    [13]

0x437808 ADD	X13, X4, #2

0x43780c LDR	D19, [X18, X13,LSL #3]    [1]

0x437810 FCMPE	D0, D19

0x437814 B.LS	437834

0x437818 ADD	W9, W2, W13

0x43781c CMP	W9, W1

0x437820 B.EQ	437834

0x437824 SBFM	X11, X8, #0, #31

0x437828 ADD	W8, W8, #1

0x43782c STR	W13, [X16, X11,LSL #2]    [7]

0x437830 STR	D19, [X15, X11,LSL #3]    [11]

0x437834 ADD	X10, X4, #3

0x437838 LDR	D20, [X18, X10,LSL #3]    [3]

0x43783c FCMPE	D0, D20

0x437840 B.LS	437860

0x437844 ADD	W14, W2, W10

0x437848 CMP	W14, W1

0x43784c B.EQ	437860

0x437850 SBFM	X12, X8, #0, #31

0x437854 ADD	W8, W8, #1

0x437858 STR	W10, [X16, X12,LSL #2]    [8]

0x43785c STR	D20, [X15, X12,LSL #3]    [13]

0x437860 ADD	X13, X4, #4

0x437864 LDR	D22, [X18, X13,LSL #3]    [4]

0x437868 FCMPE	D0, D22

0x43786c B.LS	43788c

0x437870 ADD	W9, W2, W13

0x437874 CMP	W9, W1

0x437878 B.EQ	43788c

0x43787c SBFM	X11, X8, #0, #31

0x437880 ADD	W8, W8, #1

0x437884 STR	W13, [X16, X11,LSL #2]    [7]

0x437888 STR	D22, [X15, X11,LSL #3]    [11]

0x43788c ADD	X10, X4, #5

0x437890 LDR	D24, [X18, X10,LSL #3]    [5]

0x437894 FCMPE	D0, D24

0x437898 B.LS	4378b8

0x43789c ADD	W14, W2, W10

0x4378a0 CMP	W14, W1

0x4378a4 B.EQ	4378b8

0x4378a8 SBFM	X12, X8, #0, #31

0x4378ac ADD	W8, W8, #1

0x4378b0 STR	W10, [X16, X12,LSL #2]    [8]

0x4378b4 STR	D24, [X15, X12,LSL #3]    [13]

0x4378b8 ADD	X13, X4, #6

0x4378bc LDR	D25, [X18, X13,LSL #3]    [6]

0x4378c0 FCMPE	D0, D25

0x4378c4 B.LS	4378e4

0x4378c8 ADD	W9, W2, W13

0x4378cc CMP	W9, W1

0x4378d0 B.EQ	4378e4

0x4378d4 SBFM	X11, X8, #0, #31

0x4378d8 ADD	W8, W8, #1

0x4378dc STR	W13, [X16, X11,LSL #2]    [7]

0x4378e0 STR	D25, [X15, X11,LSL #3]    [11]

0x4378e4 ADD	X4, X4, #7

0x4378e8 CMP	W3, W4

0x4378ec B.GT	437788

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 291 - 297

--------------------------------------------------------------------------------

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

Coverage (%)	Name	Source Location	Module
►50.00+	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1168	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►50.00+	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1168	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:291-297
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.25
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	11.25
CQA cycles if fully vectorized	1.67
Front-end cycles	11.25
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	10.25
P2 cycles	10.25
P3 cycles	10.25
P4 cycles	10.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.22
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.63
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:291-297
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.25
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	11.25
CQA cycles if fully vectorized	1.67
Front-end cycles	11.25
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	10.25
P2 cycles	10.25
P3 cycles	10.25
P4 cycles	10.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.22
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	17.63
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:291-297
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291-297.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6561 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 5.33 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.25 to 1.67 cycles (6.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	10.25	10.25	10.25	10.25	8.00	8.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	8.50	8.50	10.25	10.25	10.25	10.25	8.00	8.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Overall L1	11.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.25 cycles. At this rate:

5% of peak load performance is reached (5.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437788

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR D16, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4377b0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4377b0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X13, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W4, [X16, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D16, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4377dc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4377dc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W4, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D17, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437808 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437808 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D18, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437834 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437834 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D19, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437860 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437860 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D20, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D22, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 43788c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43788c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D22, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D24, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4378b8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4378b8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D24, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4378e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4378e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D25, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W3, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 437788 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:291-297
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 5.33 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	10.25	10.25	10.25	10.25	8.00	8.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	8.50	8.50	10.25	10.25	10.25	10.25	8.00	8.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Overall L1	11.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.25 cycles. At this rate:

5% of peak load performance is reached (5.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437788

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR D16, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4377b0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4377b0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X13, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W4, [X16, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D16, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4377dc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4377dc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W4, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D17, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437808 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437808 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D18, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437834 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437834 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D19, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 437860 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 437860 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D20, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D22, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 43788c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43788c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D22, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X10, X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D24, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4378b8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W14, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W14, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4378b8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X12, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W10, [X16, X12,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D24, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X13, X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X18, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4378e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4378e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W13, [X16, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D25, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X4, X4, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W3, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 437788 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code