OV - exec - Loop 635

	Loop Id: 635	Module: exec	Source: BsplineFunctor.h:305-336 [...]	Coverage: 0.06%

0x4351c8 PUNPKHI	P1.H, P3.B

0x4351cc LD1D	{Z5.D}, P1/Z, [X3, X1,LSL #3]    [40]

0x4351d0 FMUL	Z0.D, Z14.D, Z5.D

0x4351d4 MOVPRFX	Z31, Z0

0x4351d8 FCVTZS	Z31.S, P0/M, Z0.D

0x4351dc PUNPKLO	P2.H, P3.B

0x4351e0 LD1D	{Z8.D}, P2/Z, [X12, X1,LSL #3]    [21]

0x4351e4 FMUL	Z29.D, Z8.D, Z14.D

0x4351e8 MOVPRFX	Z30, Z29

0x4351ec FCVTZS	Z30.S, P0/M, Z29.D

0x4351f0 UZP1	Z2.S, Z30.S, Z31.S

0x4351f4 MOVPRFX	Z3, Z2

0x4351f8 ADD	Z3.S, Z3.S, #1

0x4351fc MOVPRFX	Z31, Z2

0x435200 ADD	Z31.S, Z31.S, #3

0x435204 SUNPKLO	Z4.D, Z3

0x435208 SUNPKLO	Z11.D, Z2

0x43520c ZIP2	Z16.S, Z2.S, Z2.S

0x435210 SUNPKHI	Z7.D, Z3

0x435214 SCVTF	Z16.D, P0/M, Z16.S

0x435218 SUNPKHI	Z3.D, Z31

0x43521c FSUB	Z1.D, Z29.D, Z16.D

0x435220 SUNPKLO	Z12.D, Z31

0x435224 MOVPRFX	Z6, Z25

0x435228 FMLA	Z6.D, P0/M, Z26.D, Z1.D

0x43522c LD1D	{Z12.D}, P2/Z, [X7, Z12.D,LSL #3]    [50]

0x435230 MOVPRFX	Z29, Z21

0x435234 FMLA	Z29.D, P0/M, Z22.D, Z1.D

0x435238 FMUL	Z31.D, Z29.D, Z12.D

0x43523c LD1D	{Z30.D}, P2/Z, [X7, Z4.D,LSL #3]    [9]

0x435240 LD1D	{Z13.D}, P2/Z, [X7, Z11.D,LSL #3]    [47]

0x435244 FMUL	Z10.D, Z6.D, Z30.D

0x435248 MOVPRFX	Z16, Z27

0x43524c FMLA	Z16.D, P0/M, Z28.D, Z1.D

0x435250 MOVPRFX	Z6, Z2

0x435254 ADD	Z6.S, Z6.S, #2

0x435258 FMAD	Z16.D, P0/M, Z13.D, Z10.D

0x43525c MOVPRFX	Z29, Z23

0x435260 FMLA	Z29.D, P0/M, Z24.D, Z1.D

0x435264 SUNPKLO	Z11.D, Z6

0x435268 ADDVL	X16, SP, #24

0x43526c LD1D	{Z11.D}, P2/Z, [X7, Z11.D,LSL #3]    [46]

0x435270 FMAD	Z29.D, P0/M, Z11.D, Z31.D

0x435274 FADD	Z31.D, Z16.D, Z29.D

0x435278 LD1D	{Z4.D}, P1/Z, [X7, Z3.D,LSL #3]    [3]

0x43527c ADD	X16, X16, #160

0x435280 SUNPKHI	Z10.D, Z2

0x435284 SUNPKHI	Z3.D, Z6

0x435288 ZIP1	Z2.S, Z2.S, Z2.S

0x43528c SCVTF	Z2.D, P0/M, Z2.S

0x435290 FSUB	Z0.D, Z0.D, Z2.D

0x435294 LDR	Z16, [X16, MUL VL]    [49]

0x435298 FMUL	Z29.D, Z31.D, Z16.D

0x43529c MOVPRFX	Z31, Z23

0x4352a0 FMLA	Z31.D, P0/M, Z24.D, Z0.D

0x4352a4 LD1D	{Z6.D}, P1/Z, [X7, Z3.D,LSL #3]    [2]

0x4352a8 LD1W	{Z9.S}, P3/Z, [X13, X1,LSL #2]    [28]

0x4352ac LD1D	{Z7.D}, P1/Z, [X7, Z7.D,LSL #3]    [18]

0x4352b0 LD1D	{Z10.D}, P1/Z, [X7, Z10.D,LSL #3]    [43]

0x4352b4 SUNPKLO	Z15.D, Z9

0x4352b8 MOVPRFX	Z3, Z21

0x4352bc FMLA	Z3.D, P0/M, Z22.D, Z0.D

0x4352c0 ST1D	{Z29.D}, P2, [X17, Z15.D,LSL #3]    [24]

0x4352c4 MOVPRFX	Z2, Z27

0x4352c8 FMLA	Z2.D, P0/M, Z28.D, Z0.D

0x4352cc MOVPRFX	Z29, Z25

0x4352d0 FMLA	Z29.D, P0/M, Z26.D, Z0.D

0x4352d4 FMUL	Z3.D, Z3.D, Z4.D

0x4352d8 ADDVL	X25, SP, #13

0x4352dc FMLA	Z3.D, P0/M, Z31.D, Z6.D

0x4352e0 ADDVL	X0, SP, #14

0x4352e4 FMUL	Z31.D, Z29.D, Z7.D

0x4352e8 ADDVL	X26, SP, #11

0x4352ec FMAD	Z2.D, P0/M, Z10.D, Z31.D

0x4352f0 ADDVL	X5, SP, #15

0x4352f4 FADD	Z2.D, Z2.D, Z3.D

0x4352f8 FMUL	Z16.D, Z2.D, Z16.D

0x4352fc SUNPKHI	Z9.D, Z9

0x435300 ADD	X25, X25, #160

0x435304 ST1D	{Z16.D}, P1, [X17, Z9.D,LSL #3]    [8]

0x435308 ADD	X0, X0, #160

0x43530c ADD	X26, X26, #160

0x435310 ADD	X5, X5, #160

0x435314 FDUP	Z3.D, #112

0x435318 ADDVL	X11, SP, #10

0x43531c ADDVL	X10, SP, #12

0x435320 ADDVL	X16, SP, #20

0x435324 LDR	Z31, [X0, MUL VL]    [42]

0x435328 LDR	Z2, [X26, MUL VL]    [44]

0x43532c LDR	Z16, [X5, MUL VL]    [26]

0x435330 ADD	X11, X11, #160

0x435334 ADD	X10, X10, #160

0x435338 ADD	X16, X16, #160

0x43533c FDIVR	Z8.D, P0/M, Z8.D, Z3.D

0x435340 ADDVL	X9, SP, #19

0x435344 FMUL	Z3.D, Z1.D, Z1.D

0x435348 LDR	Z29, [X25, MUL VL]    [27]

0x43534c ADDVL	X25, SP, #21

0x435350 FMLA	Z29.D, P0/M, Z31.D, Z1.D

0x435354 FMLA	Z29.D, P0/M, Z16.D, Z3.D

0x435358 LDR	Z31, [X11, MUL VL]    [7]

0x43535c FMLA	Z31.D, P0/M, Z2.D, Z1.D

0x435360 LDR	Z16, [X16, MUL VL]    [6]

0x435364 LDR	Z2, [X10, MUL VL]    [52]

0x435368 ADD	X9, X9, #160

0x43536c FMLA	Z31.D, P0/M, Z2.D, Z3.D

0x435370 ADD	X25, X25, #160

0x435374 ADDVL	X11, SP, #17

0x435378 LDR	Z2, [X9, MUL VL]    [45]

0x43537c FMLA	Z2.D, P0/M, Z16.D, Z1.D

0x435380 LDR	Z16, [X25, MUL VL]    [38]

0x435384 FMUL	Z31.D, Z31.D, Z12.D

0x435388 FMLA	Z2.D, P0/M, Z16.D, Z3.D

0x43538c ADD	X11, X11, #160

0x435390 ADDVL	X0, SP, #16

0x435394 ADDVL	X26, SP, #18

0x435398 LDR	Z16, [X11, MUL VL]    [17]

0x43539c FMAD	Z29.D, P0/M, Z11.D, Z31.D

0x4353a0 ADD	X0, X0, #160

0x4353a4 ADD	X26, X26, #160

0x4353a8 LDR	Z31, [X0, MUL VL]    [25]

0x4353ac FMLA	Z31.D, P0/M, Z16.D, Z1.D

0x4353b0 LDR	Z16, [X26, MUL VL]    [37]

0x4353b4 FMLA	Z31.D, P0/M, Z16.D, Z3.D

0x4353b8 FMUL	Z31.D, Z31.D, Z30.D

0x4353bc FMAD	Z2.D, P0/M, Z13.D, Z31.D

0x4353c0 ADDVL	X10, SP, #14

0x4353c4 FADD	Z29.D, Z2.D, Z29.D

0x4353c8 ADDVL	X16, SP, #11

0x4353cc FDUP	Z2.D, #112

0x4353d0 FMUL	Z8.D, Z8.D, Z14.D

0x4353d4 FDIVR	Z5.D, P0/M, Z5.D, Z2.D

0x4353d8 FMUL	Z8.D, Z29.D, Z8.D

0x4353dc ADD	X10, X10, #160

0x4353e0 ST1D	{Z8.D}, P2, [X18, Z15.D,LSL #3]    [41]

0x4353e4 ADD	X16, X16, #160

0x4353e8 FMUL	Z8.D, Z5.D, Z14.D

0x4353ec ADDVL	X5, SP, #13

0x4353f0 ADDVL	X9, SP, #10

0x4353f4 ADDVL	X25, SP, #15

0x4353f8 ADDVL	X0, SP, #12

0x4353fc LDR	Z5, [X10, MUL VL]    [1]

0x435400 LDR	Z16, [X16, MUL VL]    [36]

0x435404 ADD	X5, X5, #160

0x435408 ADD	X9, X9, #160

0x43540c ADD	X25, X25, #160

0x435410 ADD	X0, X0, #160

0x435414 LDR	Z29, [X5, MUL VL]    [4]

0x435418 ADDVL	X26, SP, #20

0x43541c FMLA	Z29.D, P0/M, Z5.D, Z0.D

0x435420 LDR	Z31, [X9, MUL VL]    [51]

0x435424 FMLA	Z31.D, P0/M, Z16.D, Z0.D

0x435428 LDR	Z5, [X25, MUL VL]    [5]

0x43542c LDR	Z16, [X0, MUL VL]    [29]

0x435430 FMUL	Z2.D, Z0.D, Z0.D

0x435434 ADD	X26, X26, #160

0x435438 FMLA	Z31.D, P0/M, Z16.D, Z2.D

0x43543c ADDVL	X11, SP, #19

0x435440 ADDVL	X5, SP, #21

0x435444 LDR	Z16, [X26, MUL VL]    [48]

0x435448 FMLA	Z29.D, P0/M, Z5.D, Z2.D

0x43544c ADD	X11, X11, #160

0x435450 ADD	X5, X5, #160

0x435454 ADDVL	X9, SP, #17

0x435458 LDR	Z5, [X11, MUL VL]    [31]

0x43545c FMLA	Z5.D, P0/M, Z16.D, Z0.D

0x435460 LDR	Z16, [X5, MUL VL]    [33]

0x435464 FMUL	Z31.D, Z31.D, Z4.D

0x435468 FMLA	Z5.D, P0/M, Z16.D, Z2.D

0x43546c ADD	X9, X9, #160

0x435470 ADDVL	X10, SP, #16

0x435474 LDR	Z16, [X9, MUL VL]    [19]

0x435478 ADDVL	X16, SP, #18

0x43547c FMAD	Z29.D, P0/M, Z6.D, Z31.D

0x435480 ADD	X10, X10, #160

0x435484 ADD	X16, X16, #160

0x435488 LDR	Z31, [X10, MUL VL]    [15]

0x43548c FMLA	Z31.D, P0/M, Z16.D, Z0.D

0x435490 LDR	Z16, [X16, MUL VL]    [39]

0x435494 FMLA	Z31.D, P0/M, Z16.D, Z2.D

0x435498 FMUL	Z31.D, Z31.D, Z7.D

0x43549c ADD	X0, SP, #160

0x4354a0 FMAD	Z5.D, P0/M, Z10.D, Z31.D

0x4354a4 FADD	Z29.D, Z5.D, Z29.D

0x4354a8 FMUL	Z8.D, Z29.D, Z8.D

0x4354ac ST1D	{Z8.D}, P1, [X18, Z9.D,LSL #3]    [34]

0x4354b0 LDR	Z31, [X0, #4, MUL VL]    [35]

0x4354b4 LDR	Z5, [X0, #3, MUL VL]    [35]

0x4354b8 ADDVL	X25, SP, #23

0x4354bc FMLA	Z5.D, P0/M, Z31.D, Z1.D

0x4354c0 ADDVL	X11, SP, #9

0x4354c4 LDR	Z31, [X0, #5, MUL VL]    [35]

0x4354c8 FMUL	Z29.D, Z3.D, Z1.D

0x4354cc ADD	X26, SP, #160

0x4354d0 ADD	X25, X25, #160

0x4354d4 LDR	Z16, [X25, MUL VL]    [32]

0x4354d8 INCB	X0, ALL, MUL #8

0x4354dc FMUL	Z8.D, Z16.D, Z3.D

0x4354e0 ADD	X11, X11, #160

0x4354e4 FMLA	Z8.D, P0/M, Z31.D, Z29.D

0x4354e8 FADD	Z8.D, Z5.D, Z8.D

0x4354ec FMUL	Z8.D, Z8.D, Z30.D

0x4354f0 LDR	Z30, [X26, #7, MUL VL]    [12]

0x4354f4 LDR	Z5, [X11, MUL VL]    [16]

0x4354f8 LDR	Z31, [X0, MUL VL]    [20]

0x4354fc FMUL	Z31.D, Z31.D, Z3.D

0x435500 FMLA	Z31.D, P0/M, Z5.D, Z29.D

0x435504 ADD	X10, SP, #160

0x435508 LDR	Z5, [X26, #6, MUL VL]    [12]

0x43550c ADDVL	X5, X26, #22

0x435510 FMLA	Z5.D, P0/M, Z30.D, Z1.D

0x435514 FMUL	Z30.D, Z19.D, Z3.D

0x435518 FADD	Z5.D, Z5.D, Z31.D

0x43551c FMLA	Z30.D, P0/M, Z20.D, Z29.D

0x435520 LDR	Z31, [X10, #2, MUL VL]    [23]

0x435524 FMAD	Z5.D, P0/M, Z13.D, Z8.D

0x435528 MOVPRFX	Z8, Z17

0x43552c FMLA	Z8.D, P0/M, Z1.D, Z18.D

0x435530 FADD	Z8.D, Z8.D, Z30.D

0x435534 LDR	Z13, [X5, MUL VL]    [11]

0x435538 FMUL	Z3.D, Z13.D, Z3.D

0x43553c FMAD	Z29.D, P0/M, Z31.D, Z3.D

0x435540 FMUL	Z12.D, Z8.D, Z12.D

0x435544 LDR	Z3, [X10, #1, MUL VL]    [23]

0x435548 ADDVL	X9, SP, #9

0x43554c LDR	Z30, [X10, MUL VL]    [23]

0x435550 FMAD	Z1.D, P0/M, Z3.D, Z30.D

0x435554 FADD	Z1.D, Z1.D, Z29.D

0x435558 FMUL	Z29.D, Z16.D, Z2.D

0x43555c FMAD	Z1.D, P0/M, Z11.D, Z12.D

0x435560 FADD	Z11.D, Z5.D, Z1.D

0x435564 ST1D	{Z11.D}, P2, [X30, Z15.D,LSL #3]    [10]

0x435568 FMUL	Z15.D, Z2.D, Z0.D

0x43556c LDR	Z5, [X10, #4, MUL VL]    [23]

0x435570 LDR	Z31, [X10, #5, MUL VL]    [23]

0x435574 LDR	Z16, [X10, #3, MUL VL]    [23]

0x435578 FMLA	Z29.D, P0/M, Z31.D, Z15.D

0x43557c FMLA	Z16.D, P0/M, Z5.D, Z0.D

0x435580 INCB	X10, ALL, MUL #8

0x435584 LDR	Z8, [X10, MUL VL]    [13]

0x435588 ADD	X16, SP, #160

0x43558c FMUL	Z3.D, Z8.D, Z2.D

0x435590 FADD	Z30.D, Z16.D, Z29.D

0x435594 LDR	Z11, [X16, #7, MUL VL]    [30]

0x435598 FMUL	Z1.D, Z30.D, Z7.D

0x43559c FMUL	Z29.D, Z19.D, Z2.D

0x4355a0 LDR	Z7, [X16, #6, MUL VL]    [30]

0x4355a4 FMLA	Z29.D, P0/M, Z20.D, Z15.D

0x4355a8 FMLA	Z7.D, P0/M, Z11.D, Z0.D

0x4355ac LDR	Z31, [X16, #1, MUL VL]    [30]

0x4355b0 ADD	X9, X9, #160

0x4355b4 LDR	Z8, [X16, MUL VL]    [30]

0x4355b8 LDR	Z12, [X9, MUL VL]    [14]

0x4355bc FMLA	Z3.D, P0/M, Z12.D, Z15.D

0x4355c0 FADD	Z16.D, Z7.D, Z3.D

0x4355c4 FMAD	Z16.D, P0/M, Z10.D, Z1.D

0x4355c8 FMUL	Z10.D, Z13.D, Z2.D

0x4355cc MOVPRFX	Z2, Z17

0x4355d0 FMLA	Z2.D, P0/M, Z0.D, Z18.D

0x4355d4 LDR	Z13, [X16, #2, MUL VL]    [30]

0x4355d8 FADD	Z5.D, Z29.D, Z2.D

0x4355dc FMAD	Z15.D, P0/M, Z13.D, Z10.D

0x4355e0 FMAD	Z0.D, P0/M, Z31.D, Z8.D

0x4355e4 FMUL	Z4.D, Z4.D, Z5.D

0x4355e8 FADD	Z0.D, Z0.D, Z15.D

0x4355ec FMAD	Z0.D, P0/M, Z6.D, Z4.D

0x4355f0 FADD	Z6.D, Z0.D, Z16.D

0x4355f4 ST1D	{Z6.D}, P1, [X30, Z9.D,LSL #3]    [22]

0x4355f8 ADD	X1, X1, X4

0x4355fc WHILELO	P3.S, W1, W8

0x435600 B.NE	4351c8

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

/usr/include/c++/11/bits/stl_vector.h: 1061 - 1061

--------------------------------------------------------------------------------

1061:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

Coverage (%)	Name	Source Location	Module
►28.57+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:312	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►28.57+	miniqmcreference::TwoBodyJastr[...]	stl_iterator.h:1007	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::TwoBodyJastr[...]	stl_iterator.h:1007	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::TwoBodyJastr[...]	stl_iterator.h:1007	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:312	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336,stl_vector.h:1061-1061
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.50
CQA cycles if no scalar integer	69.50
CQA cycles if FP arith vectorized	69.50
CQA cycles if fully vectorized	68.53
Front-end cycles	33.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	11.00
P2 cycles	11.00
P3 cycles	34.00
P4 cycles	11.00
P5 cycles	69.50
P6 cycles	69.50
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	32.00
P10 cycles	32.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	271.00
Nb uops	271.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.86
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.47
Bytes prefetched	0.00
Bytes loaded	1856.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.83
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	25.00
Vector-efficiency ratio all	98.20
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.76

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336,stl_vector.h:1061-1061
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	69.50
CQA cycles if no scalar integer	69.50
CQA cycles if FP arith vectorized	69.50
CQA cycles if fully vectorized	68.53
Front-end cycles	33.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	11.00
P2 cycles	11.00
P3 cycles	34.00
P4 cycles	11.00
P5 cycles	69.50
P6 cycles	69.50
P7 cycles	50.00
P8 cycles	50.00
P9 cycles	32.00
P10 cycles	32.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	271.00
Nb uops	271.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	8.86
Nb FLOP add-sub	64.00
Nb FLOP mul	128.00
Nb FLOP fma	208.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.47
Bytes prefetched	0.00
Bytes loaded	1856.00
Bytes stored	192.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	86.83
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	25.00
Vector-efficiency ratio all	98.20
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.76

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/usr/include/c++/11/bits/stl_vector.h:1061

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 69.50 to 68.53 cycles (1.01x speedup).

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences
SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1856 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	271
loop length	1084
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	11.00	11.00	34.00	11.00	69.50	69.50	3.00	3.00	32.00	32.00	0.00	0.00	0.00
cycles	0.50	0.50	11.00	11.00	34.00	11.00	69.50	69.50	50.00	50.00	32.00	32.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.88
Data deps.	1.00
Overall L1	69.50

Vectorization ratios

INT

all	74%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.50 cycles. At this rate:

27% of peak load performance is reached (26.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4351c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKHI P1.H, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z5.D}, P1/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z0.D, Z14.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z31.S, P0/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
PUNPKLO P2.H, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z8.D}, P2/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z30.S, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z2.S, Z30.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z3.S, Z3.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.S, Z31.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z4.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z11.D, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ZIP2 Z16.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z7.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z16.D, P0/M, Z16.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
SUNPKHI Z3.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z29.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z12.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z6, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z6.D, P0/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z12.D}, P2/Z, [X7, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z22.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z30.D}, P2/Z, [X7, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P2/Z, [X7, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z6.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z16.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z6.S, Z6.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z16.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z24.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z11.D, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z11.D}, P2/Z, [X7, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P1/Z, [X7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUNPKHI Z10.D, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z3.D, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ZIP1 Z2.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z2.D, P0/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z31, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z31.D, P0/M, Z24.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z6.D}, P1/Z, [X7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z9.S}, P3/Z, [X13, X1,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P1/Z, [X7, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P1/Z, [X7, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z15.D, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z3.D, P0/M, Z22.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z29.D}, P2, [X17, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z2, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P0/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X25, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z3.D, P0/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X0, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z31.D, Z29.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X26, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z2.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X5, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z16.D, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SUNPKHI Z9.D, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z16.D}, P1, [X17, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDUP Z3.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X11, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z2, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDIVR Z8.D, P0/M, Z8.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ADDVL X9, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z3.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z29, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X25, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z29.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z2, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X11, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z2, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z2.D, P0/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z2.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X0, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X10, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z29.D, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FDUP Z2.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z5.D, P0/M, Z5.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z8.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z8.D}, P2, [X18, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z8.D, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X5, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X25, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z5, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X26, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z29.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z5, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X11, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X5, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X9, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z5, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z5.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X10, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z29.D, P0/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z31, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X0, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z5.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z8.D}, P1, [X18, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z31, [X0, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z5, [X0, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X25, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z5.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X11, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z31, [X0, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X26, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z16, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
INCB X0, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z8.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z8.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z8.D, Z5.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z30, [X26, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z5, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z31.D, P0/M, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z5, [X26, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X5, X26, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z5.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z30.D, Z19.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z5.D, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z30.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z5.D, P0/M, Z13.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z8, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z8.D, P0/M, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z8.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z13, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z29.D, P0/M, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z12.D, Z8.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z3, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X9, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z30, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z1.D, P0/M, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z1.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z11.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z11.D}, P2, [X30, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z5, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z31, [X10, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z16.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X10, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z8, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z3.D, Z8.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z11, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z30.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z29.D, Z19.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z7, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z20.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z7.D, P0/M, Z11.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z8, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z3.D, P0/M, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z16.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z16.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z10.D, Z13.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z2, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P0/M, Z0.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z13, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z15.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z0.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z0.D, Z0.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z0.D, P0/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z6.D, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z6.D}, P1, [X30, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P3.S, W1, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 4351c8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336
/usr/include/c++/11/bits/stl_vector.h:1061

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

86% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 208 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences
SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 616 FP arithmetical operations:

272: addition or subtraction (208 inside FMA instructions)
336: multiply (208 inside FMA instructions)
8: divide

The binary loop is loading 1856 bytes. The binary loop is storing 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	271
loop length	1084
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	11.00	11.00	34.00	11.00	69.50	69.50	3.00	3.00	32.00	32.00	0.00	0.00	0.00
cycles	0.50	0.50	11.00	11.00	34.00	11.00	69.50	69.50	50.00	50.00	32.00	32.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.88
Data deps.	1.00
Overall L1	69.50

Vectorization ratios

INT

all	74%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	86%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.50 cycles. At this rate:

27% of peak load performance is reached (26.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4351c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUNPKHI P1.H, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z5.D}, P1/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z0.D, Z14.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z31.S, P0/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
PUNPKLO P2.H, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z8.D}, P2/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z30.S, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
UZP1 Z2.S, Z30.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z3.S, Z3.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.S, Z31.S, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z4.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z11.D, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ZIP2 Z16.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z7.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z16.D, P0/M, Z16.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
SUNPKHI Z3.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z29.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z12.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z6, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z6.D, P0/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z12.D}, P2/Z, [X7, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z22.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z29.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z30.D}, P2/Z, [X7, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P2/Z, [X7, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z6.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z16.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z6.S, Z6.S, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z16.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z24.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SUNPKLO Z11.D, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LD1D {Z11.D}, P2/Z, [X7, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P1/Z, [X7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUNPKHI Z10.D, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z3.D, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ZIP1 Z2.S, Z2.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z2.D, P0/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z31, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z31.D, P0/M, Z24.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z6.D}, P1/Z, [X7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1W {Z9.S}, P3/Z, [X13, X1,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P1/Z, [X7, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P1/Z, [X7, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z15.D, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z3.D, P0/M, Z22.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z29.D}, P2, [X17, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z2, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P0/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z29, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z29.D, P0/M, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X25, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z3.D, P0/M, Z31.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X0, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z31.D, Z29.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X26, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z2.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X5, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z16.D, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SUNPKHI Z9.D, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z16.D}, P1, [X17, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDUP Z3.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X11, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X10, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X16, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z2, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FDIVR Z8.D, P0/M, Z8.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ADDVL X9, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z3.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z29, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X25, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z29.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z2, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X11, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z2, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z2.D, P0/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z2.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X0, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X26, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z29.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X10, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FADD Z29.D, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADDVL X16, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FDUP Z2.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z5.D, P0/M, Z5.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z8.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ST1D {Z8.D}, P2, [X18, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z8.D, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDVL X5, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X25, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X0, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z5, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z29, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X26, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z29.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z5, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X26, X26, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X11, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ADDVL X5, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X5, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X9, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z5, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z5.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADDVL X10, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z16, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X16, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMAD Z29.D, P0/M, Z6.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, X10, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X16, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z31, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z16, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z31.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z31.D, Z31.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X0, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z5.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z29.D, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z29.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z8.D}, P1, [X18, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z31, [X0, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z5, [X0, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X25, SP, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z5.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADDVL X11, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z31, [X0, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X26, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X25, X25, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z16, [X25, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
INCB X0, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMUL Z8.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD X11, X11, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z8.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z8.D, Z5.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z30, [X26, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z5, [X11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z31, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z31.D, P0/M, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X10, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z5, [X26, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X5, X26, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
FMLA Z5.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z30.D, Z19.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z5.D, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z30.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X10, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z5.D, P0/M, Z13.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z8, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z8.D, P0/M, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z8.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z13, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z29.D, P0/M, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z12.D, Z8.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z3, [X10, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADDVL X9, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z30, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z1.D, P0/M, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z16.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z1.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z11.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z11.D}, P2, [X30, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z5, [X10, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z31, [X10, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z16, [X10, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z16.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
INCB X10, ALL, MUL #8	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
LDR Z8, [X10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z3.D, Z8.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z11, [X16, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z30.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z29.D, Z19.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z7, [X16, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z29.D, P0/M, Z20.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z7.D, P0/M, Z11.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X9, X9, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z8, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z12, [X9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z3.D, P0/M, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z16.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z16.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z10.D, Z13.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z2, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P0/M, Z0.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z13, [X16, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z15.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z0.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z0.D, Z0.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z0.D, P0/M, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z6.D, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z6.D}, P1, [X30, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P3.S, W1, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 4351c8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code