OV - exec - Loop 44

	Loop Id: 44	Module: exec	Source: miniqmc.cpp:422-453 [...]	Coverage: 0.02%

0x4071fc LDR	X0, [X24, #16]    [4]

0x407200 ADD	X23, X23, #24

0x407204 LDR	W16, [SP, #188]    [5]

0x407208 LDR	X12, [X0]    [3]

0x40720c ADD	W18, W16, #1

0x407210 STR	W18, [SP, #188]    [5]

0x407214 LDR	X0, [X12, #56]    [1]

0x407218 BL	479f20

0x40721c ORR	W2, WZR, W20

0x407220 ORR	X1, XZR, X19

0x407224 ORR	X0, XZR, X22

0x407228 BL	40d880

0x40722c LDR	X2, [X24, #16]    [4]

0x407230 LDR	X13, [X2]    [3]

0x407234 LDR	X0, [X13, #56]    [1]

0x407238 BL	47a180

0x40723c ORR	W1, WZR, W20

0x407240 ADD	X20, X20, #1

0x407244 ORR	X0, XZR, X19

0x407248 BL	4651e0

0x40724c CMP	W27, W20

0x407250 B.LE	407314

0x407254 ORR	W1, WZR, W20

0x407258 ORR	X0, XZR, X19

0x40725c BL	462dc0

0x407260 LDR	X9, [X24, #16]    [4]

0x407264 LDR	X8, [X9]    [3]

0x407268 LDR	X0, [X8, #40]    [1]

0x40726c BL	479f20

0x407270 ORR	X8, XZR, X26

0x407274 ORR	W2, WZR, W20

0x407278 ORR	X1, XZR, X19

0x40727c ORR	X0, XZR, X22

0x407280 BL	40d520

0x407284 LDR	X1, [X24, #16]    [4]

0x407288 LDR	X15, [X1]    [3]

0x40728c LDR	X0, [X15, #40]    [1]

0x407290 BL	47a180

0x407294 ORR	X2, XZR, X23

0x407298 ORR	W1, WZR, W20

0x40729c ORR	X0, XZR, X19

0x4072a0 BL	463070

0x4072a4 LDR	X11, [X24, #16]    [4]

0x4072a8 LDR	X14, [X11]    [3]

0x4072ac LDR	X0, [X14, #48]    [1]

0x4072b0 BL	479f20

0x4072b4 ORR	X3, XZR, X21

0x4072b8 ORR	W2, WZR, W20

0x4072bc STP	D15, D15, [SP, #456]    [5]

0x4072c0 ORR	X1, XZR, X19

0x4072c4 ORR	X0, XZR, X22

0x4072c8 STR	D15, [SP, #472]    [5]

0x4072cc BL	40d680

0x4072d0 LDR	X10, [X24, #16]    [4]

0x4072d4 LDR	X4, [X10]    [3]

0x4072d8 LDR	X0, [X4, #48]    [1]

0x4072dc BL	47a180

0x4072e0 LDR	D28, [X28, X20,LSL #3]    [2]

0x4072e4 FCMPE	D10, D28

0x4072e8 B.GT	4071fc

0x4072ec ORR	W1, WZR, W20

0x4072f0 ORR	X0, XZR, X19

0x4072f4 BL	463164

0x4072f8 ORR	W1, WZR, W20

0x4072fc ORR	X0, XZR, X22

0x407300 ADD	X20, X20, #1

0x407304 ADD	X23, X23, #24

0x407308 BL	40da20

0x40730c CMP	W27, W20

0x407310 B.GT	407254

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 422 - 453

--------------------------------------------------------------------------------

422:         for (int iel = 0; iel < nels; ++iel)

423:         {

424:           // Operate on electron with index iel

425:           els.setActive(iel);

426:           // Compute gradient at the current position

427:           Timers[Timer_evalGrad].get().start();

428:           PosType grad_now = wavefunction.evalGrad(els, iel);

429:           Timers[Timer_evalGrad].get().stop();

430:

431:           // Construct trial move

432:           els.makeMove(iel, delta[iel]);

433:

434:           // Compute gradient at the trial position

435:           Timers[Timer_ratioGrad].get().start();

436:           PosType grad_new;

437:           wavefunction.ratioGrad(els, iel, grad_new);

438:           Timers[Timer_ratioGrad].get().stop();

439:

440:           // Accept/reject the trial move

441:           if (ur[iel] < accept) // MC

442:           {

443:             // Update position, and update temporary storage

444:             Timers[Timer_Update].get().start();

445:             wavefunction.acceptMove(els, iel);

446:             Timers[Timer_Update].get().stop();

447:             els.acceptMove(iel);

448:             my_accepted++;

449:           }

450:           else

451:           {

452:             els.rejectMove(iel);

453:             wavefunction.restore(iel);

/usr/include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/usr/include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module
►33.33+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►33.33+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►33.33+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.40
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks
Function	main._omp_fn.1
Source	OperatorTags.h:183-183,miniqmc.cpp:422-453,refwrap.h:338-338,stl_vector.h:1046-1046
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.20
Front-end cycles	6.75
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	8.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	8.00
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.42
P10 cycles	6.25
P11 cycles	6.33
P12 cycles	0.25
P13 cycles	0.25
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	2.50
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.36
Bytes prefetched	0.00
Bytes loaded	130.00
Bytes stored	26.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.71
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Metric	Value
CQA speedup if no scalar integer	7.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3, P4, P5,
Function	main._omp_fn.1
Source	OperatorTags.h:183-183,miniqmc.cpp:422-453,refwrap.h:338-338,stl_vector.h:1046-1046
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	1.22
Front-end cycles	6.00
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.07
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.14
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.50

Metric	Value
CQA speedup if no scalar integer	5.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P4, P5,
Function	main._omp_fn.1
Source	OperatorTags.h:183-183,miniqmc.cpp:422-453,refwrap.h:338-338,stl_vector.h:1046-1046
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	1.19
Front-end cycles	7.50
DIV/SQRT cycles	7.00
P0 cycles	7.00
P1 cycles	8.50
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.83
P10 cycles	7.50
P11 cycles	7.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.65
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	28.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:422-453
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:422-453
/usr/include/c++/11/bits/refwrap.h:338
/usr/include/c++/11/bits/stl_vector.h:1046

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.20 cycles (6.65x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.00 to 5.50 cycles (1.45x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 130 bytes. The binary loop is storing 26 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

front end

6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	8.00	8.00	8.00	8.00	1.50	1.50	0.00	0.00	6.42	6.25	6.33	0.25	0.25
cycles	6.50	6.50	8.00	8.00	8.00	8.00	1.50	1.50	0.00	0.00	6.42	6.25	6.33	0.25	0.25

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	10%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:422-453
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:422-453
/usr/include/c++/11/bits/refwrap.h:338
/usr/include/c++/11/bits/stl_vector.h:1046

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 1.00 cycles (7.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.50 to 5.00 cycles (1.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	1.50	1.50	0.00	0.00	5.00	5.00	5.00	0.00	0.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	1.50	1.50	0.00	0.00	5.00	5.00	5.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.00
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

all	7%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

14% of peak load performance is reached (13.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 407254

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 462dc0 <_ZN11qmcplusplus11ParticleSet9setActiveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X8, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40d520 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X15, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 463070 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X11, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X14, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP D15, D15, [SP, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D15, [SP, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
BL 40d680 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR D28, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D10, D28	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GT 4071fc <main._omp_fn.1+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 463164 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40da20 <_ZN11qmcplusplus12WaveFunction7restoreEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W27, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 407254 <main._omp_fn.1+0xd6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:422-453
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:422-453
/usr/include/c++/11/bits/refwrap.h:338
/usr/include/c++/11/bits/stl_vector.h:1046

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 1.50 cycles (5.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.50 to 6.00 cycles (1.42x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 156 bytes. The binary loop is storing 28 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	8.50	8.50	8.50	8.50	1.50	1.50	0.00	0.00	7.83	7.50	7.67	0.50	0.50
cycles	7.00	7.00	8.50	8.50	8.50	8.50	1.50	1.50	0.00	0.00	7.83	7.50	7.67	0.50	0.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.50
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	14%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

19% of peak load performance is reached (18.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 407254

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W16, [SP, #188]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W18, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W18, [SP, #188]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X12, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40d880 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X13, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4651e0 <_ZN11qmcplusplus11ParticleSet10acceptMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 407314 <main._omp_fn.1+0xe2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 462dc0 <_ZN11qmcplusplus11ParticleSet9setActiveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40d520 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X15, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 463070 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X14, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP D15, D15, [SP, #456]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D15, [SP, #472]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
BL 40d680 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X24, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D10, D28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 4071fc <main._omp_fn.1+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code