OV - exec - Loop 42

0x4078e0 LDR	D2, [X28, X21,LSL #3]    [1]

0x4078e4 ORR	X2, XZR, X27

0x4078e8 ORR	W1, WZR, W20

0x4078ec LDRSW	X6, [X26, #8]    [9]

0x4078f0 ORR	X0, XZR, X19

0x4078f4 LDR	X12, [X26, #24]    [9]

0x4078f8 LDR	X17, [SP, #168]    [3]

0x4078fc ADD	X8, X21, X6

0x407900 ADD	X4, X8, X6

0x407904 LDP	D7, D24, [X23, #8]    [6]

0x407908 LDR	D6, [X12, X4,LSL #3]    [10]

0x40790c LDR	D14, [X12, X8,LSL #3]    [8]

0x407910 LDR	D4, [X12, X17]    [5]

0x407914 LDR	D25, [X23], #24    [6]

0x407918 FNMSUB	D26, D24, D2, D6

0x40791c FNMSUB	D3, D7, D2, D14

0x407920 FNMSUB	D0, D25, D2, D4

0x407924 STR	D26, [SP, #472]    [3]

0x407928 STP	D0, D3, [SP, #456]    [3]

0x40792c BL	463070

0x407930 LDR	X13, [X24, #16]    [7]

0x407934 LDR	X10, [X13]    [4]

0x407938 LDR	X0, [X10, #32]    [2]

0x40793c BL	479f20

0x407940 ORR	W2, WZR, W20

0x407944 ORR	X1, XZR, X19

0x407948 ORR	X0, XZR, X22

0x40794c BL	40d78c

0x407950 LDR	X3, [X24, #16]    [7]

0x407954 LDR	X14, [X3]    [4]

0x407958 LDR	X0, [X14, #32]    [2]

0x40795c BL	47a180

0x407960 ORR	W1, WZR, W20

0x407964 ORR	X0, XZR, X19

0x407968 BL	463164

0x40796c LDR	X2, [SP, #176]    [3]

0x407970 CMP	X23, X2

0x407974 B.NE	4078e0

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 53 - 63

--------------------------------------------------------------------------------

53:     return (a - b);

[...]

63:     return (a * b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 478 - 488

--------------------------------------------------------------------------------

478:             for (int k = 0; k < nknots; k++)

479:             {

480:               PosType deltar(dist[iat] * rOnSphere[k] - displ[iat]);

481:

482:               els.makeMove(jel, deltar);

483:

484:               Timers[Timer_Value].get().start();

485:               wavefunction.ratio(els, jel);

486:               Timers[Timer_Value].get().stop();

487:

488:               els.rejectMove(jel);

/usr/include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 146 - 146

--------------------------------------------------------------------------------

146:       X[i] = base[i * offset];

/usr/include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 203 - 203

--------------------------------------------------------------------------------

203:   const Type_t operator[](size_t i) const { return Type_t(myData + i, nGhosts); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 85 - 85

--------------------------------------------------------------------------------

85:       ret[d] = op(lhs[d], rhs[d]);

Coverage (%)	Name	Source Location	Module
►55.56+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►22.22+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►11.11+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►11.11+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P10, P11, P12,
Function	main._omp_fn.1
Source	OperatorTags.h:53-53,OperatorTags.h:63-63,miniqmc.cpp:478-488,refwrap.h:338-338,TinyVector.h:146-146,stl_vector.h:1046-1046,VectorSoAContainer.h:203-203,TinyVectorOps.h:85-85
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.25
Front-end cycles	4.75
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.00
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	16.67
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.79
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P10, P11, P12,
Function	main._omp_fn.1
Source	OperatorTags.h:53-53,OperatorTags.h:63-63,miniqmc.cpp:478-488,refwrap.h:338-338,TinyVector.h:146-146,stl_vector.h:1046-1046,VectorSoAContainer.h:203-203,TinyVectorOps.h:85-85
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.25
Front-end cycles	4.75
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.00
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	16.67
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.79
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:478-488
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:53,63
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:478-488
/usr/include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:146
/usr/include/c++/11/bits/stl_vector.h:1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:203
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:85

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.25 cycles (4.80x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 2.50 cycles (2.40x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 132 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.25	4.25	4.25	4.25	1.25	1.25	1.25	1.25	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	4.25	4.25	4.25	4.25	1.25	1.25	1.25	1.25	6.00	6.00	6.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Data deps.	0.00
Overall L1	6.00

Vectorization ratios

all	14%
load	16%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

22% of peak load performance is reached (22.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4078e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D2, [X28, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDRSW X6, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X8, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D7, D24, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D14, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X12, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X23], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FNMSUB D26, D24, D2, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FNMSUB D3, D7, D2, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FNMSUB D0, D25, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D26, [SP, #472]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D0, D3, [SP, #456]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
BL 463070 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X10, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40d78c <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X14, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 463164 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4078e0 <main._omp_fn.1+0x13f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	main._omp_fn.1
Source file and lines	miniqmc.cpp:478-488
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:53,63
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:478-488
/usr/include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:146
/usr/include/c++/11/bits/stl_vector.h:1046
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:203
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:85

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.25 cycles (4.80x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 2.50 cycles (2.40x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 132 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.25	4.25	4.25	4.25	1.25	1.25	1.25	1.25	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	4.25	4.25	4.25	4.25	1.25	1.25	1.25	1.25	6.00	6.00	6.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Data deps.	0.00
Overall L1	6.00

Vectorization ratios

all	14%
load	16%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

22% of peak load performance is reached (22.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4078e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D2, [X28, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDRSW X6, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X8, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D7, D24, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D14, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X12, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X23], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FNMSUB D26, D24, D2, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FNMSUB D3, D7, D2, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FNMSUB D0, D25, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D26, [SP, #472]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D0, D3, [SP, #456]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
BL 463070 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEE>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X10, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 479f20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 40d78c <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X14, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 463164 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4078e0 <main._omp_fn.1+0x13f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code