OV - exec - Loop 1350

0x47a400 LDR	X14, [X18, #32]    [1]

0x47a404 CMP	X14, X16

0x47a408 B.NE	47a498

0x47a40c LDR	X14, [X18, #40]    [1]

0x47a410 LDR	X15, [X20, #88]    [2]

0x47a414 CMP	X14, X15

0x47a418 B.NE	47a49c

0x47a41c ORR	X19, XZR, X18

0x47a420 LDR	X18, [X18, #16]    [1]

0x47a424 CBNZ	X18, 47a400

0x47a498 ORR	X15, XZR, X16

0x47a49c CMP	X14, X15

0x47a4a0 B.GE	47a41c

0x47a4a4 LDR	X18, [X18, #24]    [1]

0x47a4a8 B	47a424

/usr/include/c++/11/bits/stl_tree.h: 779 - 1904

--------------------------------------------------------------------------------

779:       _S_left(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

788:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1902:       while (__x != 0)

1903: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

1904: 	  __y = __x, __x = _S_left(__x);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 119

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:189	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1,
Function	qmcplusplus::TimerType::stop()
Source	stl_tree.h:779-779,stl_tree.h:788-788,stl_tree.h:1902-1904,NewTimer.h:119-119
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	1.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1,
Function	qmcplusplus::TimerType::stop()
Source	stl_tree.h:779-779,stl_tree.h:788-788,stl_tree.h:1902-1904,NewTimer.h:119-119
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	1.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::TimerType::stop()
Source file and lines	stl_tree.h:779-1904
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/stl_tree.h:779,788,1902-1904
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00
cycles	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X14, [X18, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 47a498 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X14, [X18, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 47a49c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBNZ X18, 47a400 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47a41c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X18, [X18, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47a424 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::TimerType::stop()
Source file and lines	stl_tree.h:779-1904
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/stl_tree.h:779,788,1902-1904
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00
cycles	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X14, [X18, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 47a498 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X14, [X18, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 47a49c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBNZ X18, 47a400 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47a41c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X18, [X18, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47a424 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code