OV - exec - Loop 1347

	Loop Id: 1347	Module: exec	Source: NewTimer.h:119-121 [...]	Coverage: 0.02%

0x47a194 LDP	X21, X22, [SP, #32]

0x47a198 LDP	X29, X30, [SP], #96

0x47a19c RET

0x47a1a0 STP	X19, X20, [SP, #16]

0x47a1a4 ORR	X20, XZR, X0

0x47a1a8 ORR	W21, WZR, W22

0x47a1ac BL	403a30

0x47a1b0 ORR	W19, WZR, W0

0x47a1b4 CMP	W0, #0

0x47a1b8 B.LE	47a338

0x47a1bc ANDS	W1, W0, #128

0x47a1c0 SUB	W2, W0, #1

0x47a1c4 B.EQ	47a274

0x47a1c8 CMP	W1, #1

0x47a1cc B.EQ	47a25c

0x47a1d0 CMP	W1, #2

0x47a1d4 B.EQ	47a248

0x47a1d8 CMP	W1, #3

0x47a1dc B.EQ	47a234

0x47a1e0 CMP	W1, #4

0x47a1e4 B.EQ	47a220

0x47a1e8 CMP	W1, #5

0x47a1ec B.EQ	47a20c

0x47a1f0 CMP	W1, #6

0x47a1f4 B.NE	47a4ac

0x47a1f8 ORR	W0, WZR, W19

0x47a1fc SUB	W19, W19, #1

0x47a200 BL	403a50

0x47a204 CMP	W0, #0

0x47a208 CSEL	W21, W21, WZR, #0

0x47a20c ORR	W0, WZR, W19

0x47a210 SUB	W19, W19, #1

0x47a214 BL	403a50

0x47a218 CMP	W0, #0

0x47a21c CSEL	W21, W21, WZR, #0

0x47a220 ORR	W0, WZR, W19

0x47a224 SUB	W19, W19, #1

0x47a228 BL	403a50

0x47a22c CMP	W0, #0

0x47a230 CSEL	W21, W21, WZR, #0

0x47a234 ORR	W0, WZR, W19

0x47a238 SUB	W19, W19, #1

0x47a23c BL	403a50

0x47a240 CMP	W0, #0

0x47a244 CSEL	W21, W21, WZR, #0

0x47a248 ORR	W0, WZR, W19

0x47a24c SUB	W19, W19, #1

0x47a250 BL	403a50

0x47a254 CMP	W0, #0

0x47a258 CSEL	W21, W21, WZR, #0

0x47a25c ORR	W0, WZR, W19

0x47a260 BL	403a50

0x47a264 CMP	W0, #0

0x47a268 CSEL	W21, W21, WZR, #0

0x47a26c SUBS	W19, W19, #1

0x47a270 B.EQ	47a324

0x47a274 STP	X23, X24, [SP, #48]

  (1349) 0x47a278 ORR	W0, WZR, W19

  (1349) 0x47a27c SUB	W23, W19, #1

  (1349) 0x47a280 BL	403a50

  (1349) 0x47a284 ORR	W3, WZR, W0

  (1349) 0x47a288 ORR	W0, WZR, W23

  (1349) 0x47a28c CMP	W3, #0

  (1349) 0x47a290 CSEL	W24, W21, WZR, #0

  (1349) 0x47a294 BL	403a50

  (1349) 0x47a298 ORR	W4, WZR, W0

  (1349) 0x47a29c SUB	W0, W23, #1

  (1349) 0x47a2a0 CMP	W4, #0

  (1349) 0x47a2a4 CSEL	W21, W24, WZR, #0

  (1349) 0x47a2a8 BL	403a50

  (1349) 0x47a2ac ORR	W5, WZR, W0

  (1349) 0x47a2b0 SUB	W0, W19, #3

  (1349) 0x47a2b4 CMP	W5, #0

  (1349) 0x47a2b8 CSEL	W23, W21, WZR, #0

  (1349) 0x47a2bc BL	403a50

  (1349) 0x47a2c0 ORR	W6, WZR, W0

  (1349) 0x47a2c4 SUB	W0, W19, #4

  (1349) 0x47a2c8 CMP	W6, #0

  (1349) 0x47a2cc CSEL	W24, W23, WZR, #0

  (1349) 0x47a2d0 BL	403a50

  (1349) 0x47a2d4 ORR	W7, WZR, W0

  (1349) 0x47a2d8 SUB	W0, W19, #5

  (1349) 0x47a2dc CMP	W7, #0

  (1349) 0x47a2e0 CSEL	W21, W24, WZR, #0

  (1349) 0x47a2e4 BL	403a50

  (1349) 0x47a2e8 ORR	W8, WZR, W0

  (1349) 0x47a2ec SUB	W0, W19, #6

  (1349) 0x47a2f0 CMP	W8, #0

  (1349) 0x47a2f4 CSEL	W23, W21, WZR, #0

  (1349) 0x47a2f8 BL	403a50

  (1349) 0x47a2fc ORR	W9, WZR, W0

  (1349) 0x47a300 SUB	W0, W19, #7

  (1349) 0x47a304 CMP	W9, #0

  (1349) 0x47a308 CSEL	W24, W23, WZR, #0

  (1349) 0x47a30c BL	403a50

  (1349) 0x47a310 CMP	W0, #0

  (1349) 0x47a314 CSEL	W21, W24, WZR, #0

  (1349) 0x47a318 SUBS	W19, W19, #8

  (1349) 0x47a31c B.NE	47a278

0x47a320 LDP	X23, X24, [SP, #48]

0x47a324 CBNZ	W21, 47a338

0x47a338 STP	X23, X24, [SP, #48]

0x47a33c ADD	X24, X20, #112

0x47a340 STP	X25, X26, [SP, #64]

0x47a344 ADD	X25, X20, #104

0x47a348 STR	D8, [SP, #88]

0x47a34c BL	403820

0x47a350 LDP	D2, D1, [X20]

0x47a354 LDR	X0, [X20, #16]

0x47a358 LDR	X13, [X25, #16]

0x47a35c FSUB	D8, D0, S2

0x47a360 ADD	X10, X0, #1

0x47a364 STR	X10, [X20, #16]

0x47a368 FADD	D0, D1, D8

0x47a36c STR	D0, [X20, #8]

0x47a370 CBZ	X13, 47a610

0x47a3d8 ADD	X25, X20, #152

0x47a3dc ADD	X24, X20, #160

0x47a3e0 LDR	D3, [X19, #56]

0x47a3e4 LDR	X18, [X25, #16]

0x47a3e8 FADD	D4, D3, D8

0x47a3ec STR	D4, [X19, #56]

0x47a3f0 CBZ	X18, 47a69c

0x47a450 LDR	X25, [X19, #56]

0x47a454 LDR	X0, [X20, #72]

0x47a458 ADD	X18, X25, #1

0x47a45c STR	X18, [X19, #56]

0x47a460 CBZ	X0, 47a594

0x47a4ac ORR	W19, WZR, W2

0x47a4b0 BL	403a50

0x47a4b4 CMP	W0, #0

0x47a4b8 CSEL	W21, W22, WZR, #0

0x47a4bc B	47a1f8

0x47a50c ORR	X0, XZR, X21

0x47a510 MOVZ	X1, #64

0x47a514 BL	4039f0

0x47a518 B	47a3d8

0x47a594 LDP	X19, X20, [SP, #16]

0x47a598 LDP	X23, X24, [SP, #48]

0x47a59c LDP	X25, X26, [SP, #64]

0x47a5a0 LDR	D8, [SP, #88]

0x47a5a4 B	47a194

0x47a610 MOVZ	X0, #64

0x47a614 BL	403b10

0x47a618 LDP	X2, X3, [X20, #80]

0x47a61c ADD	X23, X0, #32

0x47a620 ORR	X21, XZR, X0

0x47a624 LDR	X19, [X20, #96]

0x47a628 STP	X2, X3, [X0, #32]

0x47a62c STR	XZR, [X23, #24]

0x47a630 STR	X19, [X23, #16]

0x47a634 LDR	X1, [X25, #40]

0x47a638 CBZ	X1, 47a660

0x47a660 LDR	X19, [X25, #16]

0x47a664 CBZ	X19, 47a9e4

0x47a69c MOVZ	X0, #64

0x47a6a0 BL	403b10

0x47a6a4 LDP	X4, X5, [X20, #80]

0x47a6a8 ADD	X23, X0, #32

0x47a6ac ORR	X21, XZR, X0

0x47a6b0 LDR	X19, [X20, #96]

0x47a6b4 STP	X4, X5, [X0, #32]

0x47a6b8 LDR	X3, [X25, #40]

0x47a6bc STP	X19, XZR, [X23, #16]

0x47a6c0 CBZ	X3, 47a6e8

0x47a6e8 LDR	X19, [X25, #16]

0x47a6ec CBZ	X19, 47aa50

0x47a738 CMP	X9, X8

0x47a73c B.NE	47a750

0x47a740 LDR	X9, [X23, #8]

0x47a744 LDR	X8, [X19, #40]

0x47a748 CMP	X8, X9

0x47a74c B.EQ	47a50c

0x47a750 CMP	X8, X9

0x47a754 B.GE	47a50c

0x47a758 ORR	X19, XZR, X21

0x47a75c CBZ	X2, 47ace4

0x47a760 MOVZ	W16, #0

0x47a764 CMP	X24, X2

0x47a768 CSINC	W10, WZR, WZR, #1

0x47a76c ORR	W0, W16, W10

0x47a770 ANDS	W0, W0, #448

0x47a774 B.EQ	47a98c

0x47a778 ORR	X3, XZR, X24

0x47a77c ORR	X1, XZR, X21

0x47a780 BL	4038a0

0x47a784 LDR	X24, [X25, #40]

0x47a788 ADD	X13, X24, #1

0x47a78c STR	X13, [X25, #40]

0x47a790 B	47a3d8

0x47a79c CMP	X11, X10

0x47a7a0 B.NE	47ac80

0x47a7a4 LDR	X11, [X23, #8]

0x47a7a8 LDR	X10, [X19, #40]

0x47a7ac CMP	X10, X11

0x47a7b0 B.NE	47ac80

0x47a958 CMP	X24, X26

0x47a95c CSINC	W12, WZR, WZR, #1

0x47a960 ORR	W0, W22, W12

0x47a964 ANDS	W0, W0, #448

0x47a968 B.EQ	47a9b8

0x47a96c ORR	X3, XZR, X24

0x47a970 ORR	X2, XZR, X26

0x47a974 ORR	X1, XZR, X21

0x47a978 BL	4038a0

0x47a97c LDR	X24, [X25, #40]

0x47a980 ADD	X15, X24, #1

0x47a984 STR	X15, [X25, #40]

0x47a988 B	47a450

0x47a98c LDR	X11, [X2, #32]

0x47a990 LDR	X12, [X21, #32]

0x47a994 CMP	X12, X11

0x47a998 B.NE	47a9ac

0x47a99c LDR	X12, [X23, #8]

0x47a9a0 LDR	X11, [X2, #40]

0x47a9a4 CMP	X12, X11

0x47a9a8 B.EQ	47a778

0x47a9ac CMP	X12, X11

0x47a9b0 CSINC	W0, WZR, WZR, #10

0x47a9b4 B	47a778

0x47a9b8 LDR	X13, [X21, #32]

0x47a9bc LDR	X14, [X26, #32]

0x47a9c0 CMP	X14, X13

0x47a9c4 B.NE	47a9d8

0x47a9c8 LDR	X13, [X23, #8]

0x47a9cc LDR	X14, [X26, #40]

0x47a9d0 CMP	X13, X14

0x47a9d4 B.EQ	47a96c

0x47a9d8 CMP	X13, X14

0x47a9dc CSINC	W0, WZR, WZR, #10

0x47a9e0 B	47a96c

0x47a9e4 ORR	X19, XZR, X24

0x47a9e8 LDR	X7, [X25, #24]

0x47a9ec CMP	X7, X19

0x47a9f0 B.EQ	47ac04

0x47a9f4 ORR	X0, XZR, X19

0x47a9f8 BL	403ba0

0x47a9fc ORR	X2, XZR, X19

0x47aa00 ORR	X19, XZR, X0

0x47aa04 LDR	X8, [X0, #32]

0x47aa08 LDR	X9, [X21, #32]

0x47aa0c B	47a738

0x47aa50 ORR	X19, XZR, X24

0x47aa54 LDR	X9, [X25, #24]

0x47aa58 CMP	X9, X19

0x47aa5c B.EQ	47ac10

0x47aa60 ORR	X0, XZR, X19

0x47aa64 ORR	X26, XZR, X19

0x47aa68 BL	403ba0

0x47aa6c ORR	X19, XZR, X0

0x47aa70 LDR	X10, [X0, #32]

0x47aa74 LDR	X11, [X21, #32]

0x47aa78 B	47a79c

0x47aab0 MOVZ	W22, #0

0x47aab4 B	47a958

0x47ac04 ORR	X2, XZR, X19

0x47ac08 ORR	X19, XZR, X21

0x47ac0c B	47a760

0x47ac10 ORR	X26, XZR, X19

0x47ac14 ORR	X19, XZR, X21

0x47ac18 MOVZ	W22, #0

0x47ac1c B	47a958

0x47ac80 CMP	X10, X11

0x47ac84 B.GE	47a7b4

0x47ac88 ORR	X19, XZR, X21

0x47ac8c CBNZ	X26, 47aab0

0x47ace4 MOVZ	X19, #0

0x47ace8 B	47a50c

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 98 - 120

--------------------------------------------------------------------------------

98:     bool is_true_master(true);

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       double elapsed = CLOCK()() - start_time;

105:       total_time += elapsed;

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed;

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

[...]

120: }

/usr/include/c++/11/bits/stl_tree.h: 273 - 2435

--------------------------------------------------------------------------------

273:       _Rb_tree_iterator(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

302: 	_M_node = _Rb_tree_decrement(_M_node);

303: 	return *this;

[...]

735:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

750:       { return &this->_M_impl._M_header; }

[...]

1902:       while (__x != 0)

[...]

2066:       while (__x != 0)

[...]

2075: 	  if (__j == begin())

2076: 	    return _Res(__x, __y);

2077: 	  else

2078: 	    --__j;

2079: 	}

2080:       if (_M_impl._M_key_compare(_S_key(__j._M_node), __k))

[...]

2172: 	      && _M_impl._M_key_compare(_S_key(_M_rightmost()), __k))

[...]

2201: 	      if (_S_right(__pos._M_node) == 0)

[...]

2331:       bool __insert_left = (__x != 0 || __p == _M_end()

2332: 			    || _M_impl._M_key_compare(_S_key(__z),

2333: 						      _S_key(__p)));

2334:

2335:       _Rb_tree_insert_and_rebalance(__insert_left, __z, __p,

2336: 				    this->_M_impl._M_header);

2337:       ++_M_impl._M_node_count;

2338:       return iterator(__z);

[...]

2435: 	    if (__res.second)

/usr/include/c++/11/tuple: 1771 - 1772

--------------------------------------------------------------------------------

1771:       : first(std::forward<_Args1>(std::get<_Indexes1>(__tuple1))...),

1772: 	second(std::forward<_Args2>(std::get<_Indexes2>(__tuple2))...)

/usr/include/c++/11/ext/new_allocator.h: 121 - 139

--------------------------------------------------------------------------------

121: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

139: 	::operator delete(__p

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h: 33 - 33

--------------------------------------------------------------------------------

33:     return omp_get_wtime();

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 121

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

120:       {

121:         return this->long_buckets[j] < rhs.long_buckets[j];

Coverage (%)	Name	Source Location	Module
►50.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:204	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►50.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:189	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P0, P1,
Function	qmcplusplus::TimerType::stop()
Source	NewTimer.cpp:98-111,NewTimer.cpp:120-120,stl_tree.h:273-273,stl_tree.h:302-303,stl_tree.h:735-735,stl_tree.h:750-750,stl_tree.h:1902-1902,stl_tree.h:2066-2066,stl_tree.h:2075-2075,stl_tree.h:2080-2080,stl_tree.h:2172-2172,stl_tree.h:2201-2201,stl_tree.h:2331-2331,stl_tree.h:2335-2338,stl_tree.h:2435-2435,tuple:1771-1772,new_allocator.h:121-121,new_allocator.h:139-139,Clock.h:33-33,NewTimer.h:119-121
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.50
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	31.50
CQA cycles if fully vectorized	4.44
Front-end cycles	28.25
DIV/SQRT cycles	31.50
P0 cycles	31.50
P1 cycles	29.50
P2 cycles	29.50
P3 cycles	29.50
P4 cycles	29.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	19.33
P10 cycles	19.33
P11 cycles	19.33
P12 cycles	6.50
P13 cycles	6.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	226.00
Nb uops	226.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.10
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.79
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	184.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.04
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.92
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.08

Metric	Value
CQA speedup if no scalar integer	6.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P0, P1,
Function	qmcplusplus::TimerType::stop()
Source	NewTimer.cpp:98-111,NewTimer.cpp:120-120,stl_tree.h:273-273,stl_tree.h:302-303,stl_tree.h:735-735,stl_tree.h:750-750,stl_tree.h:1902-1902,stl_tree.h:2066-2066,stl_tree.h:2075-2075,stl_tree.h:2080-2080,stl_tree.h:2172-2172,stl_tree.h:2201-2201,stl_tree.h:2331-2331,stl_tree.h:2335-2338,stl_tree.h:2435-2435,tuple:1771-1772,new_allocator.h:121-121,new_allocator.h:139-139,Clock.h:33-33,NewTimer.h:119-121
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.50
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	31.50
CQA cycles if fully vectorized	4.44
Front-end cycles	28.25
DIV/SQRT cycles	31.50
P0 cycles	31.50
P1 cycles	29.50
P2 cycles	29.50
P3 cycles	29.50
P4 cycles	29.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	19.33
P10 cycles	19.33
P11 cycles	19.33
P12 cycles	6.50
P13 cycles	6.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	226.00
Nb uops	226.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.10
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.79
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	184.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.04
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.92
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.08

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::TimerType::stop()
Source file and lines	NewTimer.h:119-121
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:98-111,120
/usr/include/c++/11/bits/stl_tree.h:273,302-303,735,750,1902,2066,2075-2080,2172,2201,2331-2338,2435
/usr/include/c++/11/tuple:1771-1772
/usr/include/c++/11/ext/new_allocator.h:121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-121

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.50 to 5.00 cycles (6.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.50 to 4.44 cycles (7.10x speedup).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 31.50 to 8.00 cycles (3.94x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 408 bytes. The binary loop is storing 184 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	226
loop length	904
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	31.50	31.50	29.50	29.50	29.50	29.50	1.50	1.50	1.50	1.50	19.33	19.33	19.33	6.50	6.50
cycles	31.50	31.50	29.50	29.50	29.50	29.50	1.50	1.50	1.50	1.50	19.33	19.33	19.33	6.50	6.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.25
Overall L1	31.50

Vectorization ratios

all	2%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.50 cycles. At this rate:

13% of peak load performance is reached (12.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a30 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47a338 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W2, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47a274 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a25c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a248 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a234 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a220 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a20c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4ac <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a324 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBNZ W21, 47a338 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X20, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X20, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 403820 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D2, D1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D8, D0, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FADD D0, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X20, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X13, 47a610 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X25, X20, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X20, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X18, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D4, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D4, [X19, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X18, 47a69c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 47a594 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W22, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a1f8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039f0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47a3d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 47a194 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X3, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X1, 47a660 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47a9e4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X4, X5, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X4, X5, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X3, 47a6e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47aa50 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a750 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X2, 47ace4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W10, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W0, W0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a98c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a3d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W12, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, W22, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W0, W0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a9b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x838>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a450 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a9ac <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a778 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W0, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a778 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a9d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a96c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W0, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a96c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ac04 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a738 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ac10 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a79c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a958 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a958 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X26, 47aab0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x930>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::TimerType::stop()
Source file and lines	NewTimer.h:119-121
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:98-111,120
/usr/include/c++/11/bits/stl_tree.h:273,302-303,735,750,1902,2066,2075-2080,2172,2201,2331-2338,2435
/usr/include/c++/11/tuple:1771-1772
/usr/include/c++/11/ext/new_allocator.h:121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-121

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.50 to 5.00 cycles (6.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 31.50 to 8.00 cycles (3.94x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 408 bytes. The binary loop is storing 184 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	226
loop length	904
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	31.50	31.50	29.50	29.50	29.50	29.50	1.50	1.50	1.50	1.50	19.33	19.33	19.33	6.50	6.50
cycles	31.50	31.50	29.50	29.50	29.50	29.50	1.50	1.50	1.50	1.50	19.33	19.33	19.33	6.50	6.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.25
Overall L1	31.50

Vectorization ratios

all	2%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.50 cycles. At this rate:

13% of peak load performance is reached (12.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a30 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47a338 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W2, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47a274 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a25c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a248 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a234 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a220 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a20c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4ac <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W21, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a324 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBNZ W21, 47a338 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X20, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X20, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 403820 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D2, D1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D8, D0, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FADD D0, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X20, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X13, 47a610 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X25, X20, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X20, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X18, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D4, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D4, [X19, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X18, 47a69c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 47a594 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W21, W22, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a1f8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039f0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47a3d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 47a194 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X3, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X1, 47a660 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47a9e4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X4, X5, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X4, X5, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X3, 47a6e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47aa50 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a750 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X2, 47ace4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W10, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, W16, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W0, W0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a98c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a3d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W12, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W0, W22, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W0, W0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a9b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x838>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a450 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a9ac <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a778 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W0, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a778 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a9d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a96c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W0, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a96c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ac04 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a738 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ac10 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a79c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a958 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a958 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X26, 47aab0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x930>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a50c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code