OV - exec - Loop 1345

	Loop Id: 1345	Module: exec	Source: NewTimer.cpp:53-81 [...]	Coverage: 0.02%

0x479f94 ORR	W0, WZR, W20

0x479f98 SUB	W20, W20, #1

0x479f9c BL	403a50

0x479fa0 CMP	W0, #0

0x479fa4 CSEL	W19, W19, WZR, #0

0x479fa8 ORR	W0, WZR, W20

0x479fac SUB	W20, W20, #1

0x479fb0 BL	403a50

0x479fb4 CMP	W0, #0

0x479fb8 CSEL	W19, W19, WZR, #0

0x479fbc ORR	W0, WZR, W20

0x479fc0 SUB	W20, W20, #1

0x479fc4 BL	403a50

0x479fc8 CMP	W0, #0

0x479fcc CSEL	W19, W19, WZR, #0

0x479fd0 ORR	W0, WZR, W20

0x479fd4 SUB	W20, W20, #1

0x479fd8 BL	403a50

0x479fdc CMP	W0, #0

0x479fe0 CSEL	W19, W19, WZR, #0

0x479fe4 ORR	W0, WZR, W20

0x479fe8 SUB	W20, W20, #1

0x479fec BL	403a50

0x479ff0 CMP	W0, #0

0x479ff4 CSEL	W19, W19, WZR, #0

0x479ff8 ORR	W0, WZR, W20

0x479ffc BL	403a50

0x47a000 CMP	W0, #0

0x47a004 CSEL	W19, W19, WZR, #0

0x47a008 SUBS	W20, W20, #1

0x47a00c B.EQ	47a0b8

  (1346) 0x47a010 ORR	W0, WZR, W20

  (1346) 0x47a014 SUB	W22, W20, #1

  (1346) 0x47a018 BL	403a50

  (1346) 0x47a01c ORR	W3, WZR, W0

  (1346) 0x47a020 ORR	W0, WZR, W22

  (1346) 0x47a024 CMP	W3, #0

  (1346) 0x47a028 CSEL	W19, W19, WZR, #0

  (1346) 0x47a02c BL	403a50

  (1346) 0x47a030 ORR	W4, WZR, W0

  (1346) 0x47a034 SUB	W0, W22, #1

  (1346) 0x47a038 CMP	W4, #0

  (1346) 0x47a03c CSEL	W22, W19, WZR, #0

  (1346) 0x47a040 BL	403a50

  (1346) 0x47a044 ORR	W5, WZR, W0

  (1346) 0x47a048 SUB	W0, W20, #3

  (1346) 0x47a04c CMP	W5, #0

  (1346) 0x47a050 CSEL	W19, W22, WZR, #0

  (1346) 0x47a054 BL	403a50

  (1346) 0x47a058 ORR	W6, WZR, W0

  (1346) 0x47a05c SUB	W0, W20, #4

  (1346) 0x47a060 CMP	W6, #0

  (1346) 0x47a064 CSEL	W22, W19, WZR, #0

  (1346) 0x47a068 BL	403a50

  (1346) 0x47a06c ORR	W7, WZR, W0

  (1346) 0x47a070 SUB	W0, W20, #5

  (1346) 0x47a074 CMP	W7, #0

  (1346) 0x47a078 CSEL	W19, W22, WZR, #0

  (1346) 0x47a07c BL	403a50

  (1346) 0x47a080 ORR	W8, WZR, W0

  (1346) 0x47a084 SUB	W0, W20, #6

  (1346) 0x47a088 CMP	W8, #0

  (1346) 0x47a08c CSEL	W22, W19, WZR, #0

  (1346) 0x47a090 BL	403a50

  (1346) 0x47a094 ORR	W9, WZR, W0

  (1346) 0x47a098 SUB	W0, W20, #7

  (1346) 0x47a09c CMP	W9, #0

  (1346) 0x47a0a0 CSEL	W19, W22, WZR, #0

  (1346) 0x47a0a4 BL	403a50

  (1346) 0x47a0a8 CMP	W0, #0

  (1346) 0x47a0ac CSEL	W19, W19, WZR, #0

  (1346) 0x47a0b0 SUBS	W20, W20, #8

  (1346) 0x47a0b4 B.NE	47a010

0x47a0b8 CBNZ	W19, 47a0cc

0x47a0cc LDR	X0, [X21, #72]

0x47a0d0 CBZ	X0, 47a11c

0x47a11c BL	403820

0x47a120 STR	D0, [X21]

0x47a124 LDP	X19, X20, [SP, #16]

0x47a128 LDP	X21, X22, [SP, #32]

0x47a12c LDP	X29, X30, [SP], #48

0x47a130 RET

0x47a134 ORR	W20, WZR, W2

0x47a138 BL	403a50

0x47a13c CMP	W0, #0

0x47a140 CSEL	W19, W19, WZR, #0

0x47a144 B	479f94

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 53 - 81

--------------------------------------------------------------------------------

53:     for (int level = omp_get_level(); level > 0; level--)

54:       if (omp_get_ancestor_thread_num(level) != 0)

55:         is_true_master = false;

56:     if (is_true_master)

57:     {

58:       if (manager)

[...]

75:       start_time = CLOCK()();

[...]

81: }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h: 33 - 33

--------------------------------------------------------------------------------

33:     return omp_get_wtime();

Coverage (%)	Name	Source Location	Module
►50.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:199	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►50.00+	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:1043	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::TimerType::start()
Source	NewTimer.cpp:53-58,NewTimer.cpp:75-75,NewTimer.cpp:81-81,Clock.h:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	1.09
Front-end cycles	5.63
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.31
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.39
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P2, P3, P4, P5,
Function	qmcplusplus::TimerType::start()
Source	NewTimer.cpp:53-58,NewTimer.cpp:75-75,NewTimer.cpp:81-81,Clock.h:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	1.09
Front-end cycles	5.63
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.31
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.39
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::TimerType::start()
Source file and lines	NewTimer.cpp:53-81
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:53-58,75,81
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 1.75 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.75 to 1.09 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.75 to 4.00 cycles (2.19x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	8.75	8.75	8.75	8.75	0.50	0.50	0.00	0.00	1.83	1.50	1.67	0.00	0.00
cycles	6.50	6.50	8.75	8.75	8.75	8.75	0.50	0.50	0.00	0.00	1.83	1.50	1.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	8.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a11c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUBS W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 47a0b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W19, 47a0cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X21, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X0, 47a11c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
BL 403820 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
STR D0, [X21]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 479f94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::TimerType::start()
Source file and lines	NewTimer.cpp:53-81
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:53-58,75,81
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 1.75 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.75 to 4.00 cycles (2.19x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	8.75	8.75	8.75	8.75	0.50	0.50	0.00	0.00	1.83	1.50	1.67	0.00	0.00
cycles	6.50	6.50	8.75	8.75	8.75	8.75	0.50	0.50	0.00	0.00	1.83	1.50	1.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	8.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47a11c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W0, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUBS W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 47a0b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W19, 47a0cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X21, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X0, 47a11c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
BL 403820 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
STR D0, [X21]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403a50 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W19, W19, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 479f94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code