OV - exec - Function qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)

	Function: qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)	Module: exec	Source: WaveFunction.cpp:213-222 [...]	Coverage: 0.01%

/usr/include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 213 - 222

--------------------------------------------------------------------------------

213: {

214:   valT ratio = (iat < nelup ? Det_up->ratio(P, iat) : Det_dn->ratio(P, iat));

215:

216:   for (size_t i = 0; i < Jastrows.size(); i++)

217:   {

218:     ScopedTimer local_timer(jastrow_timers[i]);

219:     ratio *= Jastrows[i]->ratio(P, iat);

220:   }

221:   return ratio;

222: }

/usr/include/c++/11/bits/stl_vector.h: 919 - 919

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

0x40d78c STP	X29, X30, [SP, #944]!

0x40d790 ADD	X29, SP, #0

0x40d794 STP	X21, X22, [SP, #32]

0x40d798 ORR	X22, XZR, X0

0x40d79c LDR	W0, [X0, #52]

0x40d7a0 STP	X19, X20, [SP, #16]

0x40d7a4 STP	X23, X24, [SP, #48]

0x40d7a8 ORR	W23, WZR, W2

0x40d7ac ORR	X24, XZR, X1

0x40d7b0 STR	D8, [SP, #64]

0x40d7b4 CMP	W0, W2

0x40d7b8 B.LE	40d854

0x40d7bc LDR	X0, [X22]

0x40d7c0 LDR	X5, [X0]

0x40d7c4 LDR	X6, [X5, #48]

0x40d7c8 BLR	X6

0x40d7cc FMOV	D8, D0

(138) 0x40d7d0 LDR	X2, [X22, #16]

(138) 0x40d7d4 ADD	X20, X22, #16

(138) 0x40d7d8 MOVZ	X19, #0

(138) 0x40d7dc ADD	X22, X22, #88

(138) 0x40d7e0 LDR	X1, [X20, #8]

(138) 0x40d7e4 CMP	X1, X2

(138) 0x40d7e8 B.EQ	40d838

  (139) 0x40d7ec LDR	X7, [X22]

  (139) 0x40d7f0 LDR	X21, [X7, X19,LSL #3]

  (139) 0x40d7f4 ORR	X0, XZR, X21

  (139) 0x40d7f8 BL	479f20

  (139) 0x40d7fc LDR	X8, [X20]

  (139) 0x40d800 ORR	W2, WZR, W23

  (139) 0x40d804 ORR	X1, XZR, X24

  (139) 0x40d808 LDR	X0, [X8, X19,LSL #3]

  (139) 0x40d80c LDR	X9, [X0]

  (139) 0x40d810 LDR	X10, [X9, #48]

  (139) 0x40d814 BLR	X10

  (139) 0x40d818 FMUL	D8, D8, D0

  (139) 0x40d81c ORR	X0, XZR, X21

  (139) 0x40d820 ADD	X19, X19, #1

  (139) 0x40d824 BL	47a180

  (139) 0x40d828 LDP	X11, X12, [X20]

  (139) 0x40d82c SUB	X13, X12, X11

  (139) 0x40d830 CMP	X19, X13,ASR #3

  (139) 0x40d834 B.CC	40d7ec

(138) 0x40d838 FMOV	D0, D8

(138) 0x40d83c LDP	X19, X20, [SP, #16]

(138) 0x40d840 LDP	X21, X22, [SP, #32]

(138) 0x40d844 LDP	X23, X24, [SP, #48]

(138) 0x40d848 LDR	D8, [SP, #64]

(138) 0x40d84c LDP	X29, X30, [SP], #80

(138) 0x40d850 RET

(138) 0x40d854 LDR	X0, [X22, #8]

(138) 0x40d858 LDR	X3, [X0]

(138) 0x40d85c LDR	X4, [X3, #48]

(138) 0x40d860 BLR	X4

(138) 0x40d864 FMOV	D8, D0

(138) 0x40d868 B	40d7d0

0x40d86c ORR	X23, XZR, X0

0x40d870 ORR	X0, XZR, X21

0x40d874 BL	47a180

0x40d878 ORR	X0, XZR, X23

0x40d87c BL	403aa0

Coverage (%)	Name	Source Location	Module
►100.00+	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:213-222
Module	exec

The function is defined in:

/usr/include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:213-222
/usr/include/c++/11/bits/stl_vector.h:919
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.17 to 0.83 cycles (3.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.17 to 0.47 cycles (6.76x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.17 to 1.50 cycles (2.11x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	3.17	2.83	3.00	2.00	2.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	3.17	2.83	3.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	3.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.17 cycles. At this rate:

9% of peak load performance is reached (8.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d78c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W23, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40d854 <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X6	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	WaveFunction.cpp:213-222
Module	exec

The function is defined in:

/usr/include/c++/11/bits/refwrap.h:338
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:213-222
/usr/include/c++/11/bits/stl_vector.h:919
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.17 to 0.83 cycles (3.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.17 to 1.50 cycles (2.11x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	3.17	2.83	3.00	2.00	2.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.50	0.50	0.50	0.50	3.17	2.83	3.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	3.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.17 cycles. At this rate:

9% of peak load performance is reached (8.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d78c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W23, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40d854 <_ZN11qmcplusplus12WaveFunction5ratioERNS_11ParticleSetEi+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X6	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼qmcplusplus::WaveFunction::ratio(qmcplusplus::ParticleSet&, int)–	0.01	0
▼Loop 138 - WaveFunction.cpp:214-222 - exec–	0	0
○Loop 139 - WaveFunction.cpp:216-219 - exec	0.01	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code