OV - exec - Function qmcplusplus::TimerManager<qmcplusplus::TimerType<qmcplusplus::CPUClock> >::pop_timer(qmcplusplus::TimerType<qmcplusplus::CPUClock>*)

	Function: qmcplusplus::TimerManager<qmcplusplus::TimerType<qmcplusplus::CPUClock> >::pop_timer(qmcpl ...	Module: exec	Source: TimerManager.cpp:91-108 [...]	Coverage: 0.01%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.cpp: 91 - 108

--------------------------------------------------------------------------------

91: void TimerManager<TIMER>::pop_timer(TIMER* t)

92: {

93:   TIMER* stack_top = current_timer();

94:   if (stack_top == nullptr)

95:   {

96:     std::cerr << "Timer stack pop failed on an empty stack! Requested \"" << t->get_name() << "\"." << std::endl;

97:     throw std::runtime_error("TimerManager pop_timer error!");

98:   }

99:   else if (t != stack_top)

100:   {

101:     std::cerr << "Timer stack pop not matching push! "

102:               << "Expecting \"" << t->get_name() << "\" but \"" << stack_top->get_name() << "\" is on the top."

103:               << std::endl;

104:     throw std::runtime_error("TimerManager pop_timer error!");

105:   }

106:   else

107:     CurrentTimerStack.pop_back();

108: }

/usr/include/c++/11/bits/char_traits.h: 329 - 409

--------------------------------------------------------------------------------

329:       { __c1 = __c2; }

[...]

403: 	if (__n == 0)

[...]

409: 	return static_cast<char_type*>(__builtin_memcpy(__s1, __s2, __n));

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h: 92 - 93

--------------------------------------------------------------------------------

92:     if (CurrentTimerStack.size() > 0)

93:       current = CurrentTimerStack.back();

/usr/include/c++/11/bits/basic_ios.h: 49 - 50

--------------------------------------------------------------------------------

49:       if (!__f)

50: 	__throw_bad_cast();

/usr/include/c++/11/ostream: 113 - 704

--------------------------------------------------------------------------------

113: 	return __pf(*this);

[...]

611: 	__ostream_insert(__out, __s,

[...]

682:     { return flush(__os.put(__os.widen('\n'))); }

[...]

704:     { return __os.flush(); }

/usr/include/c++/11/bits/locale_facets.h: 877 - 880

--------------------------------------------------------------------------------

877: 	if (_M_widen_ok)

878: 	  return _M_widen[static_cast<unsigned char>(__c)];

879: 	this->_M_widen_init();

880: 	return this->do_widen(__c);

/usr/include/c++/11/bits/stl_vector.h: 919 - 1228

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1228: 	--this->_M_impl._M_finish;

/usr/include/c++/11/ext/new_allocator.h: 89 - 139

--------------------------------------------------------------------------------

89:       ~new_allocator() _GLIBCXX_USE_NOEXCEPT { }

[...]

139: 	::operator delete(__p

/usr/include/c++/11/bits/basic_string.h: 160 - 6522

--------------------------------------------------------------------------------

160: 	: allocator_type(std::move(__a)), _M_p(__dat) { }

[...]

179:       { _M_dataplus._M_p = __p; }

180:

181:       void

182:       _M_length(size_type __length)

183:       { _M_string_length = __length; }

184:

185:       pointer

186:       _M_data() const

187:       { return _M_dataplus._M_p; }

[...]

211:       { _M_allocated_capacity = __capacity; }

[...]

231: 	if (!_M_is_local())

[...]

237:       { _Alloc_traits::deallocate(_M_get_allocator(), _M_data(), __size + 1); }

[...]

348: 	if (__n == 1)

[...]

658:       { _M_dispose(); }

[...]

913:       { return _M_string_length; }

[...]

6522:       return __ostream_insert(__os, __str.data(), __str.size());

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 190 - 190

--------------------------------------------------------------------------------

190:   inline std::string get_name() const { return name; }

/usr/include/c++/11/bits/basic_string.tcc: 211 - 232

--------------------------------------------------------------------------------

211: 	if (__gnu_cxx::__is_null_pointer(__beg) && __beg != __end)

212: 	  std::__throw_logic_error(__N("basic_string::"

213: 				       "_M_construct null not valid"));

214:

215: 	size_type __dnew = static_cast<size_type>(std::distance(__beg, __end));

216:

217: 	if (__dnew > size_type(_S_local_capacity))

218: 	  {

219: 	    _M_data(_M_create(__dnew, size_type(0)));

[...]

232: 	_M_set_length(__dnew);

0x47f160 ADRP	X3,

0x47f164 STP	X29, X30, [SP, #880]!

0x47f168 ADD	X29, SP, #0

0x47f16c ADD	X4, X0, #72

0x47f170 LDR	X2, [X3, #4016]

0x47f174 STP	X19, X20, [SP, #16]

0x47f178 ORR	X19, XZR, X1

0x47f17c LDR	X0, [X0, #72]

0x47f180 LDR	X1, [X2]

0x47f184 STR	X1, [SP, #136]

0x47f188 MOVZ	X1, #0

0x47f18c LDR	X1, [X4, #8]

0x47f190 CMP	X1, X0

0x47f194 B.EQ	47f1d8

0x47f198 LDUR	X20, [X1, #504]

0x47f19c CBZ	X20, 47f1d8

0x47f1a0 CMP	X19, X20

0x47f1a4 B.NE	47f354

0x47f1a8 ADRP	X5,

0x47f1ac SUB	X6, X1, #8

0x47f1b0 LDR	X7, [X5, #4016]

0x47f1b4 STR	X6, [X4, #8]

0x47f1b8 LDR	X2, [SP, #136]

0x47f1bc LDR	X1, [X7]

0x47f1c0 SUBS	X2, X2, X1

0x47f1c4 MOVZ	X1, #0

0x47f1c8 B.NE	47f348

0x47f1cc LDP	X19, X20, [SP, #16]

0x47f1d0 LDP	X29, X30, [SP], #144

0x47f1d4 RET

0x47f1d8 ADRP	X15,

0x47f1dc STP	X21, X22, [SP, #32]

0x47f1e0 ADRP	X22,

0x47f1e4 ADD	X1, X15, #1336

0x47f1e8 MOVZ	X2, #53

0x47f1ec ADD	X21, SP, #120

0x47f1f0 LDR	X0, [X22, #4056]

0x47f1f4 STR	X23, [SP, #48]

0x47f1f8 ADD	X23, SP, #104

0x47f1fc BL	4039e0

0x47f200 LDP	X20, X19, [X19, #24]

0x47f204 STR	X21, [SP, #104]

0x47f208 CMN	X20, X19

0x47f20c CCMP	X20, #0, #0, #1

0x47f210 B.EQ	47f40c

0x47f214 STR	X19, [SP, #64]

0x47f218 CMP	X19, #15

0x47f21c B.HI	47f314

0x47f220 CMP	X19, #1

0x47f224 B.NE	47f304

0x47f228 LDRB	W16, [X20]

0x47f22c ORR	X3, XZR, X21

0x47f230 STRB	W16, [SP, #120]

0x47f234 STR	X19, [SP, #112]

0x47f238 LDR	X0, [X22, #4056]

0x47f23c STRB	WZR, [X3, X19]

0x47f240 LDP	X1, X2, [SP, #104]

0x47f244 BL	4039e0

0x47f248 ADRP	X17,

0x47f24c MOVZ	X2, #2

0x47f250 ADD	X1, X17, #1392

0x47f254 ORR	X22, XZR, X0

0x47f258 BL	4039e0

0x47f25c LDR	X30, [X22]

0x47f260 LDUR	X2, [X30, #488]

0x47f264 ADD	X4, X22, X2

0x47f268 LDR	X20, [X4, #240]

0x47f26c CBZ	X20, 47f408

0x47f270 LDRB	W0, [X20, #56]

0x47f274 CBZ	W0, 47f2d0

0x47f278 LDRB	W1, [X20, #67]

(1412) 0x47f27c ORR	X0, XZR, X22

(1412) 0x47f280 BL	403b60

(1412) 0x47f284 BL	403d50

(1412) 0x47f288 LDR	X0, [SP, #104]

(1412) 0x47f28c CMP	X0, X21

(1412) 0x47f290 B.EQ	47f2a0

(1412) 0x47f294 LDR	X23, [SP, #120]

(1412) 0x47f298 ADD	X1, X23, #1

(1412) 0x47f29c BL	4039f0

(1412) 0x47f2a0 MOVZ	X0, #16

(1412) 0x47f2a4 BL	403cb0

(1412) 0x47f2a8 ADRP	X1,

(1412) 0x47f2ac ORR	X19, XZR, X0

(1412) 0x47f2b0 ADD	X1, X1, #1400

(1412) 0x47f2b4 BL	4038c0

(1412) 0x47f2b8 ADRP	X9,

(1412) 0x47f2bc ADRP	X10,

(1412) 0x47f2c0 LDR	X2, [X9, #3840]

(1412) 0x47f2c4 ORR	X0, XZR, X19

(1412) 0x47f2c8 LDR	X1, [X10, #3920]

(1412) 0x47f2cc BL	403d20

(1412) 0x47f2d0 ORR	X0, XZR, X20

(1412) 0x47f2d4 BL	403900

(1412) 0x47f2d8 LDR	X7, [X20]

(1412) 0x47f2dc ADRP	X5,

(1412) 0x47f2e0 MOVZ	W1, #10

(1412) 0x47f2e4 ADD	X6, X5, #1504

(1412) 0x47f2e8 LDR	X8, [X7, #48]

(1412) 0x47f2ec CMP	X8, X6

(1412) 0x47f2f0 B.EQ	47f27c

(1412) 0x47f2f4 ORR	X0, XZR, X20

(1412) 0x47f2f8 BLR	X8

(1412) 0x47f2fc AND	W1, W0, #448

(1412) 0x47f300 B	47f27c

0x47f304 ORR	X3, XZR, X21

0x47f308 CBZ	X19, 47f234

0x47f30c ORR	X0, XZR, X21

0x47f310 B	47f330

0x47f314 MOVZ	X2, #0

0x47f318 ADD	X1, SP, #64

0x47f31c ORR	X0, XZR, X23

0x47f320 BL	403970

0x47f324 LDR	X18, [SP, #64]

0x47f328 STR	X0, [SP, #104]

0x47f32c STR	X18, [SP, #120]

0x47f330 ORR	X2, XZR, X19

0x47f334 ORR	X1, XZR, X20

0x47f338 BL	4039b0

0x47f33c LDR	X19, [SP, #64]

0x47f340 LDR	X3, [SP, #104]

0x47f344 B	47f234

0x47f348 STP	X21, X22, [SP, #32]

0x47f34c STR	X23, [SP, #48]

0x47f350 BL	403d80

0x47f354 ADRP	X8,

0x47f358 ADRP	X9,

0x47f35c STP	X21, X22, [SP, #32]

0x47f360 ADD	X1, X8, #1432

0x47f364 ADD	X21, SP, #72

0x47f368 LDR	X0, [X9, #4056]

0x47f36c BL	403930

0x47f370 ADRP	X10,

0x47f374 ADD	X1, X10, #1472

0x47f378 BL	403930

0x47f37c ORR	X11, XZR, X0

0x47f380 ADD	X1, X19, #24

0x47f384 ORR	X0, XZR, X21

0x47f388 ORR	X22, XZR, X11

0x47f38c BL	403c20

0x47f390 ORR	X0, XZR, X22

0x47f394 LDP	X1, X2, [SP, #72]

0x47f398 BL	4039e0

0x47f39c ADRP	X12,

0x47f3a0 ADD	X1, X12, #1488

0x47f3a4 BL	403930

0x47f3a8 ADD	X22, SP, #104

0x47f3ac ORR	X19, XZR, X0

0x47f3b0 ADD	X1, X20, #24

0x47f3b4 ORR	X0, XZR, X22

0x47f3b8 BL	403c20

0x47f3bc ORR	X0, XZR, X19

0x47f3c0 LDP	X1, X2, [SP, #104]

0x47f3c4 BL	4039e0

0x47f3c8 ADRP	X13,

0x47f3cc ADD	X1, X13, #1496

0x47f3d0 BL	403930

0x47f3d4 BL	47ba00

0x47f3d8 ORR	X0, XZR, X22

0x47f3dc BL	403730

0x47f3e0 ORR	X0, XZR, X21

0x47f3e4 BL	403730

0x47f3e8 MOVZ	X0, #16

0x47f3ec BL	403cb0

0x47f3f0 ADRP	X14,

0x47f3f4 ORR	X19, XZR, X0

0x47f3f8 ADD	X1, X14, #1400

0x47f3fc BL	4038c0

0x47f400 STR	X23, [SP, #48]

0x47f404 B	47f2b8

0x47f408 BL	403a60

0x47f40c ADRP	X12, 49d40c

0x47f410 ADD	X0, X12, #3656

0x47f414 BL	403b00

0x47f418 ORR	X11, XZR, X0

0x47f41c ORR	X0, XZR, X19

0x47f420 ORR	X21, XZR, X11

0x47f424 BL	403c60

0x47f428 ORR	X0, XZR, X21

0x47f42c BL	403aa0

0x47f430 ORR	X19, XZR, X0

0x47f434 ORR	X0, XZR, X23

0x47f438 BL	403730

0x47f43c ORR	X0, XZR, X19

0x47f440 BL	403aa0

0x47f444 ORR	X20, XZR, X0

0x47f448 ORR	X0, XZR, X22

0x47f44c BL	403730

(1411) 0x47f450 ORR	X0, XZR, X21

(1411) 0x47f454 STR	X23, [SP, #48]

(1411) 0x47f458 BL	403730

(1411) 0x47f45c ORR	X0, XZR, X20

(1411) 0x47f460 BL	403aa0

(1411) 0x47f464 ORR	X20, XZR, X0

(1411) 0x47f468 B	47f450

0x47f46c STR	X23, [SP, #48]

0x47f470 B	47f418

0x47f474 HINT	#0

0x47f478 HINT	#0

0x47f47c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:194	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	TimerManager.cpp:91-108
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.cpp:91-108
/usr/include/c++/11/bits/char_traits.h:329,403,409
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/usr/include/c++/11/bits/basic_ios.h:49-50
/usr/include/c++/11/ostream:113,611,682,704
/usr/include/c++/11/bits/locale_facets.h:877-880
/usr/include/c++/11/bits/stl_vector.h:919,1228
/usr/include/c++/11/ext/new_allocator.h:89,139
/usr/include/c++/11/bits/basic_string.h:160,179-187,211,231,237,348,658,913,6522
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:190
/usr/include/c++/11/bits/basic_string.tcc:211-219,232

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 24.50 to 6.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 13.00 cycles (1.88x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 235 bytes. The binary function is storing 170 bytes.

General properties

nb instructions	159
loop length	636
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	20.50	20.50	24.50	24.50	24.50	24.50	0.00	0.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00
cycles	20.50	20.50	24.50	24.50	24.50	24.50	0.00	0.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.50
Overall L1	24.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

9% of peak load performance is reached (9.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47f160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X3, <4c1160>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X0, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X3, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47f1d8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X20, 47f1d8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47f354 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X5, <4c11a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X5, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.NE 47f348 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X15, <4a01d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X22, <4c11e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, #1336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #53	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMN X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X20, #0, #0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47f40c <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X19, #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 47f314 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47f304 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X22, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STRB WZR, [X3, X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X17, <4a0248>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X17, #1392	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X2, [X30, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X22, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X4, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X20, 47f408 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W0, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W0, 47f2d0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W1, [X20, #67]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X19, 47f234 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47f330 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403970 <@plt_start@+0x2f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47f234 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403d80 <@plt_start@+0x700>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4a0354>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X9, <4c1358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X8, #1432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X9, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X10, <4a0370>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X10, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c20 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <4a039c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, #1488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X22, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c20 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X13, <4a03c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X13, #1496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 47ba00 <_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.isra.0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X14, <4a03f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47f2b8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 403a60 <@plt_start@+0x3e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, 49d40c <_ZN8tinyxml211XMLDocument18CreateUnlinkedNodeINS_7XMLTextELi112EEEPT_RNS_8MemPoolTIXT0_EEE+0x8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #3656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b00 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c60 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47f418 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	TimerManager.cpp:91-108
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.cpp:91-108
/usr/include/c++/11/bits/char_traits.h:329,403,409
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/usr/include/c++/11/bits/basic_ios.h:49-50
/usr/include/c++/11/ostream:113,611,682,704
/usr/include/c++/11/bits/locale_facets.h:877-880
/usr/include/c++/11/bits/stl_vector.h:919,1228
/usr/include/c++/11/ext/new_allocator.h:89,139
/usr/include/c++/11/bits/basic_string.h:160,179-187,211,231,237,348,658,913,6522
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:190
/usr/include/c++/11/bits/basic_string.tcc:211-219,232

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 13.00 cycles (1.88x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 235 bytes. The binary function is storing 170 bytes.

General properties

nb instructions	159
loop length	636
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	20.50	20.50	24.50	24.50	24.50	24.50	0.00	0.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00
cycles	20.50	20.50	24.50	24.50	24.50	24.50	0.00	0.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.50
Overall L1	24.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

9% of peak load performance is reached (9.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47f160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X3, <4c1160>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X0, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X3, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47f1d8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X20, 47f1d8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47f354 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X5, <4c11a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X5, #4016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.NE 47f348 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X15, <4a01d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X22, <4c11e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, #1336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #53	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X23, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMN X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X20, #0, #0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47f40c <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X19, #15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 47f314 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47f304 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X22, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STRB WZR, [X3, X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X17, <4a0248>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X17, #1392	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X2, [X30, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X22, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X4, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X20, 47f408 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W0, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W0, 47f2d0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRB W1, [X20, #67]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X19, 47f234 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47f330 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403970 <@plt_start@+0x2f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039b0 <@plt_start@+0x330>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47f234 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403d80 <@plt_start@+0x700>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4a0354>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X9, <4c1358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X8, #1432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X9, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X10, <4a0370>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X10, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c20 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <4a039c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, #1488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X22, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c20 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 4039e0 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X13, <4a03c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X13, #1496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403930 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 47ba00 <_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.isra.0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X14, <4a03f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47f2b8 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 403a60 <@plt_start@+0x3e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, 49d40c <_ZN8tinyxml211XMLDocument18CreateUnlinkedNodeINS_7XMLTextELi112EEEPT_RNS_8MemPoolTIXT0_EEE+0x8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #3656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b00 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c60 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403aa0 <@plt_start@+0x420>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403730 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47f418 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerManager >::pop_timer(qmcplusplus::TimerType*)–	0.01	0
○Loop 1412 - locale_facets.h:879-880 - exec	0	0
○Loop 1411 - basic_string.h:658-658 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code