OV - exec - Function qmcplusplus::TimerType<qmcplusplus::CPUClock>::stop()

	Function: qmcplusplus::TimerType<qmcplusplus::CPUClock>::stop()	Module: exec	Source: NewTimer.cpp:84-120 [...]	Coverage: 0.06%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 84 - 120

--------------------------------------------------------------------------------

84: void TimerType<CLOCK>::stop()

85: {

86:   if (active)

[...]

98:     bool is_true_master(true);

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       double elapsed = CLOCK()() - start_time;

105:       total_time += elapsed;

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed;

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/usr/include/c++/11/bits/stl_tree.h: 273 - 2435

--------------------------------------------------------------------------------

273:       _Rb_tree_iterator(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

287: 	_M_node = _Rb_tree_increment(_M_node);

[...]

302: 	_M_node = _Rb_tree_decrement(_M_node);

303: 	return *this;

[...]

735:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

750:       { return &this->_M_impl._M_header; }

[...]

779:       _S_left(_Base_ptr __x) _GLIBCXX_NOEXCEPT

780:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

788:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1902:       while (__x != 0)

1903: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

1904: 	  __y = __x, __x = _S_left(__x);

[...]

2066:       while (__x != 0)

2067: 	{

2068: 	  __y = __x;

2069: 	  __comp = _M_impl._M_key_compare(__k, _S_key(__x));

2070: 	  __x = __comp ? _S_left(__x) : _S_right(__x);

2071: 	}

2072:       iterator __j = iterator(__y);

2073:       if (__comp)

2074: 	{

2075: 	  if (__j == begin())

2076: 	    return _Res(__x, __y);

2077: 	  else

2078: 	    --__j;

2079: 	}

2080:       if (_M_impl._M_key_compare(_S_key(__j._M_node), __k))

2081: 	return _Res(__x, __y);

[...]

2172: 	      && _M_impl._M_key_compare(_S_key(_M_rightmost()), __k))

2173: 	    return _Res(0, _M_rightmost());

2174: 	  else

2175: 	    return _M_get_insert_unique_pos(__k);

2176: 	}

2177:       else if (_M_impl._M_key_compare(__k, _S_key(__pos._M_node)))

2178: 	{

2179: 	  // First, try before...

2180: 	  iterator __before = __pos;

2181: 	  if (__pos._M_node == _M_leftmost()) // begin()

2182: 	    return _Res(_M_leftmost(), _M_leftmost());

2183: 	  else if (_M_impl._M_key_compare(_S_key((--__before)._M_node), __k))

2184: 	    {

2185: 	      if (_S_right(__before._M_node) == 0)

[...]

2193:       else if (_M_impl._M_key_compare(_S_key(__pos._M_node), __k))

2194: 	{

2195: 	  // ... then try after.

2196: 	  iterator __after = __pos;

2197: 	  if (__pos._M_node == _M_rightmost())

2198: 	    return _Res(0, _M_rightmost());

2199: 	  else if (_M_impl._M_key_compare(__k, _S_key((++__after)._M_node)))

2200: 	    {

2201: 	      if (_S_right(__pos._M_node) == 0)

[...]

2331:       bool __insert_left = (__x != 0 || __p == _M_end()

2332: 			    || _M_impl._M_key_compare(_S_key(__z),

2333: 						      _S_key(__p)));

2334:

2335:       _Rb_tree_insert_and_rebalance(__insert_left, __z, __p,

2336: 				    this->_M_impl._M_header);

2337:       ++_M_impl._M_node_count;

2338:       return iterator(__z);

[...]

2435: 	    if (__res.second)

/usr/include/c++/11/tuple: 1771 - 1772

--------------------------------------------------------------------------------

1771:       : first(std::forward<_Args1>(std::get<_Indexes1>(__tuple1))...),

1772: 	second(std::forward<_Args2>(std::get<_Indexes2>(__tuple2))...)

/usr/include/c++/11/bits/stl_map.h: 499 - 499

--------------------------------------------------------------------------------

499: 	if (__i == end() || key_comp()(__k, (*__i).first))

/usr/include/c++/11/ext/new_allocator.h: 121 - 139

--------------------------------------------------------------------------------

121: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

139: 	::operator delete(__p

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h: 33 - 33

--------------------------------------------------------------------------------

33:     return omp_get_wtime();

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 121

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

120:       {

121:         return this->long_buckets[j] < rhs.long_buckets[j];

0x47a180 STP	X29, X30, [SP, #928]!

0x47a184 ADD	X29, SP, #0

0x47a188 STP	X21, X22, [SP, #32]

0x47a18c LDRB	W22, [X0, #56]

0x47a190 CBNZ	W22, 47a1a0

  (1347) 0x47a194 LDP	X21, X22, [SP, #32]

  (1347) 0x47a198 LDP	X29, X30, [SP], #96

  (1347) 0x47a19c RET

  (1347) 0x47a1a0 STP	X19, X20, [SP, #16]

  (1347) 0x47a1a4 ORR	X20, XZR, X0

  (1347) 0x47a1a8 ORR	W21, WZR, W22

  (1347) 0x47a1ac BL	403a30

  (1347) 0x47a1b0 ORR	W19, WZR, W0

  (1347) 0x47a1b4 CMP	W0, #0

  (1347) 0x47a1b8 B.LE	47a338

  (1347) 0x47a1bc ANDS	W1, W0, #128

  (1347) 0x47a1c0 SUB	W2, W0, #1

  (1347) 0x47a1c4 B.EQ	47a274

  (1347) 0x47a1c8 CMP	W1, #1

  (1347) 0x47a1cc B.EQ	47a25c

  (1347) 0x47a1d0 CMP	W1, #2

  (1347) 0x47a1d4 B.EQ	47a248

  (1347) 0x47a1d8 CMP	W1, #3

  (1347) 0x47a1dc B.EQ	47a234

  (1347) 0x47a1e0 CMP	W1, #4

  (1347) 0x47a1e4 B.EQ	47a220

  (1347) 0x47a1e8 CMP	W1, #5

  (1347) 0x47a1ec B.EQ	47a20c

  (1347) 0x47a1f0 CMP	W1, #6

  (1347) 0x47a1f4 B.NE	47a4ac

  (1347) 0x47a1f8 ORR	W0, WZR, W19

  (1347) 0x47a1fc SUB	W19, W19, #1

  (1347) 0x47a200 BL	403a50

  (1347) 0x47a204 CMP	W0, #0

  (1347) 0x47a208 CSEL	W21, W21, WZR, #0

  (1347) 0x47a20c ORR	W0, WZR, W19

  (1347) 0x47a210 SUB	W19, W19, #1

  (1347) 0x47a214 BL	403a50

  (1347) 0x47a218 CMP	W0, #0

  (1347) 0x47a21c CSEL	W21, W21, WZR, #0

  (1347) 0x47a220 ORR	W0, WZR, W19

  (1347) 0x47a224 SUB	W19, W19, #1

  (1347) 0x47a228 BL	403a50

  (1347) 0x47a22c CMP	W0, #0

  (1347) 0x47a230 CSEL	W21, W21, WZR, #0

  (1347) 0x47a234 ORR	W0, WZR, W19

  (1347) 0x47a238 SUB	W19, W19, #1

  (1347) 0x47a23c BL	403a50

  (1347) 0x47a240 CMP	W0, #0

  (1347) 0x47a244 CSEL	W21, W21, WZR, #0

  (1347) 0x47a248 ORR	W0, WZR, W19

  (1347) 0x47a24c SUB	W19, W19, #1

  (1347) 0x47a250 BL	403a50

  (1347) 0x47a254 CMP	W0, #0

  (1347) 0x47a258 CSEL	W21, W21, WZR, #0

  (1347) 0x47a25c ORR	W0, WZR, W19

  (1347) 0x47a260 BL	403a50

  (1347) 0x47a264 CMP	W0, #0

  (1347) 0x47a268 CSEL	W21, W21, WZR, #0

  (1347) 0x47a26c SUBS	W19, W19, #1

  (1347) 0x47a270 B.EQ	47a324

  (1347) 0x47a274 STP	X23, X24, [SP, #48]

    (1349) 0x47a278 ORR	W0, WZR, W19

    (1349) 0x47a27c SUB	W23, W19, #1

    (1349) 0x47a280 BL	403a50

    (1349) 0x47a284 ORR	W3, WZR, W0

    (1349) 0x47a288 ORR	W0, WZR, W23

    (1349) 0x47a28c CMP	W3, #0

    (1349) 0x47a290 CSEL	W24, W21, WZR, #0

    (1349) 0x47a294 BL	403a50

    (1349) 0x47a298 ORR	W4, WZR, W0

    (1349) 0x47a29c SUB	W0, W23, #1

    (1349) 0x47a2a0 CMP	W4, #0

    (1349) 0x47a2a4 CSEL	W21, W24, WZR, #0

    (1349) 0x47a2a8 BL	403a50

    (1349) 0x47a2ac ORR	W5, WZR, W0

    (1349) 0x47a2b0 SUB	W0, W19, #3

    (1349) 0x47a2b4 CMP	W5, #0

    (1349) 0x47a2b8 CSEL	W23, W21, WZR, #0

    (1349) 0x47a2bc BL	403a50

    (1349) 0x47a2c0 ORR	W6, WZR, W0

    (1349) 0x47a2c4 SUB	W0, W19, #4

    (1349) 0x47a2c8 CMP	W6, #0

    (1349) 0x47a2cc CSEL	W24, W23, WZR, #0

    (1349) 0x47a2d0 BL	403a50

    (1349) 0x47a2d4 ORR	W7, WZR, W0

    (1349) 0x47a2d8 SUB	W0, W19, #5

    (1349) 0x47a2dc CMP	W7, #0

    (1349) 0x47a2e0 CSEL	W21, W24, WZR, #0

    (1349) 0x47a2e4 BL	403a50

    (1349) 0x47a2e8 ORR	W8, WZR, W0

    (1349) 0x47a2ec SUB	W0, W19, #6

    (1349) 0x47a2f0 CMP	W8, #0

    (1349) 0x47a2f4 CSEL	W23, W21, WZR, #0

    (1349) 0x47a2f8 BL	403a50

    (1349) 0x47a2fc ORR	W9, WZR, W0

    (1349) 0x47a300 SUB	W0, W19, #7

    (1349) 0x47a304 CMP	W9, #0

    (1349) 0x47a308 CSEL	W24, W23, WZR, #0

    (1349) 0x47a30c BL	403a50

    (1349) 0x47a310 CMP	W0, #0

    (1349) 0x47a314 CSEL	W21, W24, WZR, #0

    (1349) 0x47a318 SUBS	W19, W19, #8

    (1349) 0x47a31c B.NE	47a278

  (1347) 0x47a320 LDP	X23, X24, [SP, #48]

  (1347) 0x47a324 CBNZ	W21, 47a338

0x47a328 LDP	X19, X20, [SP, #16]

0x47a32c LDP	X21, X22, [SP, #32]

0x47a330 LDP	X29, X30, [SP], #96

0x47a334 RET

  (1347) 0x47a338 STP	X23, X24, [SP, #48]

  (1347) 0x47a33c ADD	X24, X20, #112

  (1347) 0x47a340 STP	X25, X26, [SP, #64]

  (1347) 0x47a344 ADD	X25, X20, #104

  (1347) 0x47a348 STR	D8, [SP, #88]

  (1347) 0x47a34c BL	403820

  (1347) 0x47a350 LDP	D2, D1, [X20]

  (1347) 0x47a354 LDR	X0, [X20, #16]

  (1347) 0x47a358 LDR	X13, [X25, #16]

  (1347) 0x47a35c FSUB	D8, D0, S2

  (1347) 0x47a360 ADD	X10, X0, #1

  (1347) 0x47a364 STR	X10, [X20, #16]

  (1347) 0x47a368 FADD	D0, D1, D8

  (1347) 0x47a36c STR	D0, [X20, #8]

  (1347) 0x47a370 CBZ	X13, 47a610

0x47a374 LDR	X14, [X20, #80]

0x47a378 ORR	X19, XZR, X24

0x47a37c HINT	#0

(1351) 0x47a380 LDR	X11, [X13, #32]

(1351) 0x47a384 CMP	X11, X14

(1351) 0x47a388 B.NE	47a484

(1351) 0x47a38c LDR	X11, [X13, #40]

(1351) 0x47a390 LDR	X12, [X20, #88]

(1351) 0x47a394 CMP	X11, X12

(1351) 0x47a398 B.NE	47a488

(1351) 0x47a39c ORR	X19, XZR, X13

(1351) 0x47a3a0 LDR	X13, [X13, #16]

(1351) 0x47a3a4 CBNZ	X13, 47a380

0x47a3a8 CMP	X24, X19

0x47a3ac B.EQ	47a610

0x47a3b0 STR	X27, [SP, #80]

0x47a3b4 ADD	X27, X19, #32

0x47a3b8 LDR	X15, [X19, #32]

0x47a3bc CMP	X15, X14

0x47a3c0 B.NE	47a4c0

0x47a3c4 LDR	X15, [X27, #8]

0x47a3c8 LDR	X14, [X20, #88]

0x47a3cc CMP	X14, X15

0x47a3d0 B.NE	47a4c0

0x47a3d4 LDR	X27, [SP, #80]

  (1347) 0x47a3d8 ADD	X25, X20, #152

  (1347) 0x47a3dc ADD	X24, X20, #160

  (1347) 0x47a3e0 LDR	D3, [X19, #56]

  (1347) 0x47a3e4 LDR	X18, [X25, #16]

  (1347) 0x47a3e8 FADD	D4, D3, D8

  (1347) 0x47a3ec STR	D4, [X19, #56]

  (1347) 0x47a3f0 CBZ	X18, 47a69c

0x47a3f4 LDR	X16, [X20, #80]

0x47a3f8 ORR	X19, XZR, X24

0x47a3fc HINT	#0

(1350) 0x47a400 LDR	X14, [X18, #32]

(1350) 0x47a404 CMP	X14, X16

(1350) 0x47a408 B.NE	47a498

(1350) 0x47a40c LDR	X14, [X18, #40]

(1350) 0x47a410 LDR	X15, [X20, #88]

(1350) 0x47a414 CMP	X14, X15

(1350) 0x47a418 B.NE	47a49c

(1350) 0x47a41c ORR	X19, XZR, X18

(1350) 0x47a420 LDR	X18, [X18, #16]

(1350) 0x47a424 CBNZ	X18, 47a400

0x47a428 CMP	X19, X24

0x47a42c B.EQ	47a69c

0x47a430 LDR	X2, [X19, #32]

0x47a434 ADD	X26, X19, #32

0x47a438 CMP	X2, X16

0x47a43c B.NE	47a7fc

0x47a440 LDR	X2, [X26, #8]

0x47a444 LDR	X16, [X20, #88]

0x47a448 CMP	X16, X2

0x47a44c B.NE	47a7fc

  (1347) 0x47a450 LDR	X25, [X19, #56]

  (1347) 0x47a454 LDR	X0, [X20, #72]

  (1347) 0x47a458 ADD	X18, X25, #1

  (1347) 0x47a45c STR	X18, [X19, #56]

  (1347) 0x47a460 CBZ	X0, 47a594

0x47a464 ORR	X1, XZR, X20

0x47a468 LDP	X19, X20, [SP, #16]

0x47a46c LDP	X21, X22, [SP, #32]

0x47a470 LDP	X23, X24, [SP, #48]

0x47a474 LDP	X25, X26, [SP, #64]

0x47a478 LDR	D8, [SP, #88]

0x47a47c LDP	X29, X30, [SP], #96

0x47a480 B	47f160

(1351) 0x47a484 ORR	X12, XZR, X14

(1351) 0x47a488 CMP	X11, X12

(1351) 0x47a48c B.GE	47a39c

(1351) 0x47a490 LDR	X13, [X13, #24]

(1351) 0x47a494 B	47a3a4

(1350) 0x47a498 ORR	X15, XZR, X16

(1350) 0x47a49c CMP	X14, X15

(1350) 0x47a4a0 B.GE	47a41c

(1350) 0x47a4a4 LDR	X18, [X18, #24]

(1350) 0x47a4a8 B	47a424

  (1347) 0x47a4ac ORR	W19, WZR, W2

  (1347) 0x47a4b0 BL	403a50

  (1347) 0x47a4b4 CMP	W0, #0

  (1347) 0x47a4b8 CSEL	W21, W22, WZR, #0

  (1347) 0x47a4bc B	47a1f8

0x47a4c0 CMP	X14, X15

0x47a4c4 B.GE	47a3d4

0x47a4c8 MOVZ	X0, #64

0x47a4cc BL	403b10

0x47a4d0 LDP	X26, X18, [X20, #80]

0x47a4d4 ADD	X23, X0, #32

0x47a4d8 ORR	X21, XZR, X0

0x47a4dc LDR	X1, [X20, #96]

0x47a4e0 STP	X26, X18, [X0, #32]

0x47a4e4 STP	X1, XZR, [X23, #16]

0x47a4e8 LDR	X2, [X19, #32]

0x47a4ec CMP	X26, X2

0x47a4f0 B.NE	47a51c

0x47a4f4 LDR	X16, [X23, #8]

0x47a4f8 LDR	X2, [X27, #8]

0x47a4fc CMP	X16, X2

0x47a500 B.LT	47a5a8

0x47a504 B.NE	47a524

0x47a508 LDR	X27, [SP, #80]

  (1347) 0x47a50c ORR	X0, XZR, X21

  (1347) 0x47a510 MOVZ	X1, #64

  (1347) 0x47a514 BL	4039f0

  (1347) 0x47a518 B	47a3d8

0x47a51c ORR	X16, XZR, X26

0x47a520 B.LT	47a5a8

0x47a524 CMP	X2, X16

0x47a528 B.GE	47a508

0x47a52c LDR	X8, [X20, #136]

0x47a530 CMP	X8, X19

0x47a534 B.EQ	47ab4c

0x47a538 ORR	X0, XZR, X19

0x47a53c BL	4039c0

0x47a540 LDR	X9, [X0, #32]

0x47a544 CMP	X9, X26

0x47a548 B.NE	47acc4

0x47a54c LDR	X10, [X23, #8]

0x47a550 LDR	X9, [X0, #40]

0x47a554 CMP	X10, X9

0x47a558 B.NE	47acc8

0x47a55c LDR	X19, [X25, #16]

0x47a560 CBZ	X19, 47ac20

0x47a564 LDR	X18, [X19, #32]

0x47a568 CMP	X18, X26

0x47a56c B.NE	47abc0

0x47a570 LDR	X11, [X23, #8]

0x47a574 LDR	X0, [X19, #40]

0x47a578 CMP	X11, X0

0x47a57c B.NE	47abc8

0x47a580 LDR	X13, [X19, #24]

0x47a584 MOVZ	W12, #0

0x47a588 CBZ	X13, 47ab88

0x47a58c ORR	X19, XZR, X13

0x47a590 B	47a564

  (1347) 0x47a594 LDP	X19, X20, [SP, #16]

  (1347) 0x47a598 LDP	X23, X24, [SP, #48]

  (1347) 0x47a59c LDP	X25, X26, [SP, #64]

  (1347) 0x47a5a0 LDR	D8, [SP, #88]

  (1347) 0x47a5a4 B	47a194

0x47a5a8 LDR	X27, [X20, #128]

0x47a5ac CMP	X27, X19

0x47a5b0 B.EQ	47aab8

0x47a5b4 ORR	X0, XZR, X19

0x47a5b8 BL	403ba0

0x47a5bc LDR	X3, [X0, #32]

0x47a5c0 CMP	X3, X26

0x47a5c4 B.NE	47ac50

0x47a5c8 LDR	X17, [X23, #8]

0x47a5cc LDR	X3, [X0, #40]

0x47a5d0 CMP	X3, X17

0x47a5d4 B.NE	47ac54

0x47a5d8 LDR	X19, [X25, #16]

0x47a5dc CBZ	X19, 47ab04

0x47a5e0 LDR	X18, [X19, #32]

0x47a5e4 CMP	X18, X26

0x47a5e8 B.NE	47aacc

0x47a5ec LDR	X4, [X23, #8]

0x47a5f0 LDR	X30, [X19, #40]

0x47a5f4 CMP	X4, X30

0x47a5f8 B.NE	47aad4

0x47a5fc LDR	X6, [X19, #24]

0x47a600 MOVZ	W5, #0

0x47a604 CBZ	X6, 47aa10

0x47a608 ORR	X19, XZR, X6

0x47a60c B	47a5e0

  (1347) 0x47a610 MOVZ	X0, #64

  (1347) 0x47a614 BL	403b10

  (1347) 0x47a618 LDP	X2, X3, [X20, #80]

  (1347) 0x47a61c ADD	X23, X0, #32

  (1347) 0x47a620 ORR	X21, XZR, X0

  (1347) 0x47a624 LDR	X19, [X20, #96]

  (1347) 0x47a628 STP	X2, X3, [X0, #32]

  (1347) 0x47a62c STR	XZR, [X23, #24]

  (1347) 0x47a630 STR	X19, [X23, #16]

  (1347) 0x47a634 LDR	X1, [X25, #40]

  (1347) 0x47a638 CBZ	X1, 47a660

0x47a63c LDR	X2, [X20, #136]

0x47a640 LDR	X17, [X21, #32]

0x47a644 LDR	X3, [X2, #32]

0x47a648 CMP	X3, X17

0x47a64c B.NE	47ac70

0x47a650 LDR	X17, [X23, #8]

0x47a654 LDR	X3, [X2, #40]

0x47a658 CMP	X17, X3

0x47a65c B.NE	47ac70

  (1347) 0x47a660 LDR	X19, [X25, #16]

  (1347) 0x47a664 CBZ	X19, 47a9e4

0x47a668 LDR	X9, [X21, #32]

0x47a66c LDR	X8, [X19, #32]

0x47a670 CMP	X9, X8

0x47a674 B.NE	47a7c4

0x47a678 LDR	X4, [X23, #8]

0x47a67c LDR	X30, [X19, #40]

0x47a680 CMP	X4, X30

0x47a684 B.NE	47a7cc

0x47a688 LDR	X6, [X19, #24]

0x47a68c MOVZ	W5, #0

0x47a690 CBZ	X6, 47a730

0x47a694 ORR	X19, XZR, X6

0x47a698 B	47a66c

  (1347) 0x47a69c MOVZ	X0, #64

  (1347) 0x47a6a0 BL	403b10

  (1347) 0x47a6a4 LDP	X4, X5, [X20, #80]

  (1347) 0x47a6a8 ADD	X23, X0, #32

  (1347) 0x47a6ac ORR	X21, XZR, X0

  (1347) 0x47a6b0 LDR	X19, [X20, #96]

  (1347) 0x47a6b4 STP	X4, X5, [X0, #32]

  (1347) 0x47a6b8 LDR	X3, [X25, #40]

  (1347) 0x47a6bc STP	X19, XZR, [X23, #16]

  (1347) 0x47a6c0 CBZ	X3, 47a6e8

0x47a6c4 LDR	X26, [X20, #184]

0x47a6c8 LDR	X17, [X21, #32]

0x47a6cc LDR	X5, [X26, #32]

0x47a6d0 CMP	X5, X17

0x47a6d4 B.NE	47ac94

0x47a6d8 LDR	X17, [X23, #8]

0x47a6dc LDR	X5, [X26, #40]

0x47a6e0 CMP	X5, X17

0x47a6e4 B.NE	47ac94

  (1347) 0x47a6e8 LDR	X19, [X25, #16]

  (1347) 0x47a6ec CBZ	X19, 47aa50

0x47a6f0 LDR	X11, [X21, #32]

0x47a6f4 HINT	#0

0x47a6f8 HINT	#0

0x47a6fc HINT	#0

0x47a700 LDR	X10, [X19, #32]

0x47a704 CMP	X11, X10

0x47a708 B.NE	47a7e0

0x47a70c LDR	X6, [X23, #8]

0x47a710 LDR	X30, [X19, #40]

0x47a714 CMP	X6, X30

0x47a718 B.NE	47a7e8

0x47a71c LDR	X8, [X19, #24]

0x47a720 MOVZ	W7, #0

0x47a724 CBZ	X8, 47a794

0x47a728 ORR	X19, XZR, X8

0x47a72c B	47a700

0x47a730 ORR	X2, XZR, X19

0x47a734 CBNZ	W5, 47a9e8

  (1347) 0x47a738 CMP	X9, X8

  (1347) 0x47a73c B.NE	47a750

  (1347) 0x47a740 LDR	X9, [X23, #8]

  (1347) 0x47a744 LDR	X8, [X19, #40]

  (1347) 0x47a748 CMP	X8, X9

  (1347) 0x47a74c B.EQ	47a50c

  (1347) 0x47a750 CMP	X8, X9

  (1347) 0x47a754 B.GE	47a50c

  (1347) 0x47a758 ORR	X19, XZR, X21

  (1347) 0x47a75c CBZ	X2, 47ace4

  (1347) 0x47a760 MOVZ	W16, #0

  (1347) 0x47a764 CMP	X24, X2

  (1347) 0x47a768 CSINC	W10, WZR, WZR, #1

  (1347) 0x47a76c ORR	W0, W16, W10

  (1347) 0x47a770 ANDS	W0, W0, #448

  (1347) 0x47a774 B.EQ	47a98c

  (1347) 0x47a778 ORR	X3, XZR, X24

  (1347) 0x47a77c ORR	X1, XZR, X21

  (1347) 0x47a780 BL	4038a0

  (1347) 0x47a784 LDR	X24, [X25, #40]

  (1347) 0x47a788 ADD	X13, X24, #1

  (1347) 0x47a78c STR	X13, [X25, #40]

  (1347) 0x47a790 B	47a3d8

0x47a794 ORR	X26, XZR, X19

0x47a798 CBNZ	W7, 47aa54

  (1347) 0x47a79c CMP	X11, X10

  (1347) 0x47a7a0 B.NE	47ac80

  (1347) 0x47a7a4 LDR	X11, [X23, #8]

  (1347) 0x47a7a8 LDR	X10, [X19, #40]

  (1347) 0x47a7ac CMP	X10, X11

  (1347) 0x47a7b0 B.NE	47ac80

(1348) 0x47a7b4 ORR	X0, XZR, X21

(1348) 0x47a7b8 MOVZ	X1, #64

(1348) 0x47a7bc BL	4039f0

(1348) 0x47a7c0 B	47a450

0x47a7c4 ORR	X30, XZR, X8

0x47a7c8 ORR	X4, XZR, X9

0x47a7cc CMP	X4, X30

0x47a7d0 B.GE	47a688

0x47a7d4 ORR	W5, WZR, W22

0x47a7d8 LDR	X6, [X19, #16]

0x47a7dc B	47a690

0x47a7e0 ORR	X30, XZR, X10

0x47a7e4 ORR	X6, XZR, X11

0x47a7e8 CMP	X6, X30

0x47a7ec B.GE	47a71c

0x47a7f0 ORR	W7, WZR, W22

0x47a7f4 LDR	X8, [X19, #16]

0x47a7f8 B	47a724

0x47a7fc STR	X27, [SP, #80]

0x47a800 CMP	X16, X2

0x47a804 B.GE	47ac48

0x47a808 MOVZ	X0, #64

0x47a80c BL	403b10

0x47a810 LDP	X27, X1, [X20, #80]

0x47a814 ADD	X23, X0, #32

0x47a818 ORR	X21, XZR, X0

0x47a81c LDR	X3, [X20, #96]

0x47a820 STP	X27, X1, [X0, #32]

0x47a824 STP	X3, XZR, [X23, #16]

0x47a828 LDR	X4, [X19, #32]

0x47a82c CMP	X4, X27

0x47a830 B.NE	47a850

0x47a834 LDR	X17, [X23, #8]

0x47a838 LDR	X4, [X26, #8]

0x47a83c CMP	X4, X17

0x47a840 B.GT	47a8cc

0x47a844 B.NE	47a858

0x47a848 LDR	X27, [SP, #80]

0x47a84c B	47a7b4

0x47a850 ORR	X17, XZR, X27

0x47a854 B.GT	47a8cc

0x47a858 CMP	X4, X17

0x47a85c B.GE	47a848

0x47a860 LDR	X26, [X20, #184]

0x47a864 CMP	X19, X26

0x47a868 B.EQ	47abb8

0x47a86c ORR	X0, XZR, X19

0x47a870 BL	4039c0

0x47a874 ORR	X12, XZR, X0

0x47a878 LDR	X0, [X0, #32]

0x47a87c CMP	X0, X27

0x47a880 B.NE	47aca4

0x47a884 LDR	X13, [X23, #8]

0x47a888 LDR	X0, [X12, #40]

0x47a88c CMP	X0, X13

0x47a890 B.NE	47aca8

0x47a894 LDR	X19, [X25, #16]

0x47a898 CBZ	X19, 47abdc

0x47a89c LDR	X1, [X19, #32]

0x47a8a0 CMP	X1, X27

0x47a8a4 B.NE	47ab9c

0x47a8a8 LDR	X15, [X23, #8]

0x47a8ac LDR	X14, [X19, #40]

0x47a8b0 CMP	X14, X15

0x47a8b4 B.NE	47aba4

0x47a8b8 LDR	X26, [X19, #24]

0x47a8bc MOVZ	W18, #0

0x47a8c0 CBZ	X26, 47ab54

0x47a8c4 ORR	X19, XZR, X26

0x47a8c8 B	47a89c

0x47a8cc LDR	X26, [X20, #176]

0x47a8d0 CMP	X19, X26

0x47a8d4 B.EQ	47a950

0x47a8d8 ORR	X0, XZR, X19

0x47a8dc BL	403ba0

0x47a8e0 LDR	X5, [X0, #32]

0x47a8e4 CMP	X5, X27

0x47a8e8 B.NE	47a934

0x47a8ec LDR	X30, [X23, #8]

0x47a8f0 LDR	X5, [X0, #40]

0x47a8f4 CMP	X5, X30

0x47a8f8 B.NE	47a938

0x47a8fc LDR	X19, [X25, #16]

0x47a900 CBZ	X19, 47ab28

0x47a904 LDR	X10, [X19, #32]

0x47a908 CMP	X10, X27

0x47a90c B.NE	47aae8

0x47a910 LDR	X7, [X23, #8]

0x47a914 LDR	X6, [X19, #40]

0x47a918 CMP	X6, X7

0x47a91c B.NE	47aaf0

0x47a920 LDR	X9, [X19, #24]

0x47a924 MOVZ	W8, #0

0x47a928 CBZ	X9, 47aa7c

0x47a92c ORR	X19, XZR, X9

0x47a930 B	47a904

0x47a934 ORR	X30, XZR, X27

0x47a938 CMP	X5, X30

0x47a93c B.GE	47a8fc

0x47a940 LDR	X11, [X0, #24]

0x47a944 CMP	X11, #0

0x47a948 CSEL	X26, X19, X0, #1

0x47a94c CSEL	W22, W22, WZR, #1

0x47a950 LDR	X27, [SP, #80]

0x47a954 ORR	X19, XZR, X21

  (1347) 0x47a958 CMP	X24, X26

  (1347) 0x47a95c CSINC	W12, WZR, WZR, #1

  (1347) 0x47a960 ORR	W0, W22, W12

  (1347) 0x47a964 ANDS	W0, W0, #448

  (1347) 0x47a968 B.EQ	47a9b8

  (1347) 0x47a96c ORR	X3, XZR, X24

  (1347) 0x47a970 ORR	X2, XZR, X26

  (1347) 0x47a974 ORR	X1, XZR, X21

  (1347) 0x47a978 BL	4038a0

  (1347) 0x47a97c LDR	X24, [X25, #40]

  (1347) 0x47a980 ADD	X15, X24, #1

  (1347) 0x47a984 STR	X15, [X25, #40]

  (1347) 0x47a988 B	47a450

  (1347) 0x47a98c LDR	X11, [X2, #32]

  (1347) 0x47a990 LDR	X12, [X21, #32]

  (1347) 0x47a994 CMP	X12, X11

  (1347) 0x47a998 B.NE	47a9ac

  (1347) 0x47a99c LDR	X12, [X23, #8]

  (1347) 0x47a9a0 LDR	X11, [X2, #40]

  (1347) 0x47a9a4 CMP	X12, X11

  (1347) 0x47a9a8 B.EQ	47a778

  (1347) 0x47a9ac CMP	X12, X11

  (1347) 0x47a9b0 CSINC	W0, WZR, WZR, #10

  (1347) 0x47a9b4 B	47a778

  (1347) 0x47a9b8 LDR	X13, [X21, #32]

  (1347) 0x47a9bc LDR	X14, [X26, #32]

  (1347) 0x47a9c0 CMP	X14, X13

  (1347) 0x47a9c4 B.NE	47a9d8

  (1347) 0x47a9c8 LDR	X13, [X23, #8]

  (1347) 0x47a9cc LDR	X14, [X26, #40]

  (1347) 0x47a9d0 CMP	X13, X14

  (1347) 0x47a9d4 B.EQ	47a96c

  (1347) 0x47a9d8 CMP	X13, X14

  (1347) 0x47a9dc CSINC	W0, WZR, WZR, #10

  (1347) 0x47a9e0 B	47a96c

  (1347) 0x47a9e4 ORR	X19, XZR, X24

  (1347) 0x47a9e8 LDR	X7, [X25, #24]

  (1347) 0x47a9ec CMP	X7, X19

  (1347) 0x47a9f0 B.EQ	47ac04

  (1347) 0x47a9f4 ORR	X0, XZR, X19

  (1347) 0x47a9f8 BL	403ba0

  (1347) 0x47a9fc ORR	X2, XZR, X19

  (1347) 0x47aa00 ORR	X19, XZR, X0

  (1347) 0x47aa04 LDR	X8, [X0, #32]

  (1347) 0x47aa08 LDR	X9, [X21, #32]

  (1347) 0x47aa0c B	47a738

0x47aa10 ORR	X15, XZR, X19

0x47aa14 CBNZ	W5, 47ab08

0x47aa18 CMP	X26, X18

0x47aa1c B.NE	47aa30

0x47aa20 LDR	X26, [X23, #8]

0x47aa24 LDR	X18, [X19, #40]

0x47aa28 CMP	X18, X26

0x47aa2c B.EQ	47a508

0x47aa30 CMP	X18, X26

0x47aa34 B.GE	47a508

0x47aa38 ORR	X19, XZR, X15

0x47aa3c ORR	X2, XZR, X19

0x47aa40 ORR	X19, XZR, X21

0x47aa44 LDR	X27, [SP, #80]

0x47aa48 CBNZ	X2, 47a760

0x47aa4c B	47ace4

  (1347) 0x47aa50 ORR	X19, XZR, X24

  (1347) 0x47aa54 LDR	X9, [X25, #24]

  (1347) 0x47aa58 CMP	X9, X19

  (1347) 0x47aa5c B.EQ	47ac10

  (1347) 0x47aa60 ORR	X0, XZR, X19

  (1347) 0x47aa64 ORR	X26, XZR, X19

  (1347) 0x47aa68 BL	403ba0

  (1347) 0x47aa6c ORR	X19, XZR, X0

  (1347) 0x47aa70 LDR	X10, [X0, #32]

  (1347) 0x47aa74 LDR	X11, [X21, #32]

  (1347) 0x47aa78 B	47a79c

0x47aa7c CBNZ	W8, 47ab2c

0x47aa80 ORR	X26, XZR, X19

0x47aa84 CMP	X10, X27

0x47aa88 B.NE	47aa9c

0x47aa8c LDR	X27, [X23, #8]

0x47aa90 LDR	X10, [X19, #40]

0x47aa94 CMP	X27, X10

0x47aa98 B.EQ	47a848

0x47aa9c CMP	X10, X27

0x47aaa0 B.GE	47a848

0x47aaa4 ORR	X19, XZR, X21

0x47aaa8 LDR	X27, [SP, #80]

0x47aaac CBZ	X26, 47acec

  (1347) 0x47aab0 MOVZ	W22, #0

  (1347) 0x47aab4 B	47a958

0x47aab8 ORR	W16, WZR, W22

0x47aabc ORR	X2, XZR, X19

0x47aac0 ORR	X19, XZR, X21

0x47aac4 LDR	X27, [SP, #80]

0x47aac8 B	47a764

0x47aacc ORR	X30, XZR, X18

0x47aad0 ORR	X4, XZR, X26

0x47aad4 CMP	X4, X30

0x47aad8 B.GE	47a5fc

0x47aadc ORR	W5, WZR, W22

0x47aae0 LDR	X6, [X19, #16]

0x47aae4 B	47a604

0x47aae8 ORR	X6, XZR, X10

0x47aaec ORR	X7, XZR, X27

0x47aaf0 CMP	X7, X6

0x47aaf4 B.GE	47a920

0x47aaf8 ORR	W8, WZR, W22

0x47aafc LDR	X9, [X19, #16]

0x47ab00 B	47a928

0x47ab04 ORR	X19, XZR, X24

0x47ab08 CMP	X27, X19

0x47ab0c B.EQ	47aa3c

0x47ab10 ORR	X0, XZR, X19

0x47ab14 BL	403ba0

0x47ab18 ORR	X15, XZR, X19

0x47ab1c ORR	X19, XZR, X0

0x47ab20 LDR	X18, [X0, #32]

0x47ab24 B	47aa18

0x47ab28 ORR	X19, XZR, X24

0x47ab2c CMP	X26, X19

0x47ab30 B.EQ	47aaa4

0x47ab34 ORR	X0, XZR, X19

0x47ab38 ORR	X26, XZR, X19

0x47ab3c BL	403ba0

0x47ab40 ORR	X19, XZR, X0

0x47ab44 LDR	X10, [X0, #32]

0x47ab48 B	47aa84

0x47ab4c MOVZ	W16, #0

0x47ab50 B	47aabc

0x47ab54 ORR	X2, XZR, X19

0x47ab58 CBNZ	W18, 47abe0

0x47ab5c CMP	X27, X1

0x47ab60 B.NE	47ab74

0x47ab64 LDR	X27, [X23, #8]

0x47ab68 LDR	X1, [X19, #40]

0x47ab6c CMP	X1, X27

0x47ab70 B.EQ	47a848

0x47ab74 CMP	X1, X27

0x47ab78 B.GE	47a848

0x47ab7c ORR	X19, XZR, X2

0x47ab80 ORR	X26, XZR, X19

0x47ab84 B	47aaa4

0x47ab88 ORR	X15, XZR, X19

0x47ab8c CBNZ	W12, 47ac24

0x47ab90 CMP	X18, X26

0x47ab94 B.EQ	47aa20

0x47ab98 B	47aa30

0x47ab9c ORR	X14, XZR, X1

0x47aba0 ORR	X15, XZR, X27

0x47aba4 CMP	X15, X14

0x47aba8 B.GE	47a8b8

0x47abac ORR	W18, WZR, W22

0x47abb0 LDR	X26, [X19, #16]

0x47abb4 B	47a8c0

0x47abb8 MOVZ	W22, #0

0x47abbc B	47a950

0x47abc0 ORR	X0, XZR, X18

0x47abc4 ORR	X11, XZR, X26

0x47abc8 CMP	X11, X0

0x47abcc B.GE	47a580

0x47abd0 ORR	W12, WZR, W22

0x47abd4 LDR	X13, [X19, #16]

0x47abd8 B	47a588

0x47abdc ORR	X19, XZR, X24

0x47abe0 LDR	X22, [X25, #24]

0x47abe4 CMP	X22, X19

0x47abe8 B.EQ	47ab80

0x47abec ORR	X0, XZR, X19

0x47abf0 BL	403ba0

0x47abf4 ORR	X2, XZR, X19

0x47abf8 ORR	X19, XZR, X0

0x47abfc LDR	X1, [X0, #32]

0x47ac00 B	47ab5c

  (1347) 0x47ac04 ORR	X2, XZR, X19

  (1347) 0x47ac08 ORR	X19, XZR, X21

  (1347) 0x47ac0c B	47a760

  (1347) 0x47ac10 ORR	X26, XZR, X19

  (1347) 0x47ac14 ORR	X19, XZR, X21

  (1347) 0x47ac18 MOVZ	W22, #0

  (1347) 0x47ac1c B	47a958

0x47ac20 ORR	X19, XZR, X24

0x47ac24 LDR	X14, [X25, #24]

0x47ac28 CMP	X14, X19

0x47ac2c B.EQ	47aa3c

0x47ac30 ORR	X0, XZR, X19

0x47ac34 BL	403ba0

0x47ac38 ORR	X15, XZR, X19

0x47ac3c ORR	X19, XZR, X0

0x47ac40 LDR	X18, [X0, #32]

0x47ac44 B	47ab90

0x47ac48 LDR	X27, [SP, #80]

0x47ac4c B	47a450

0x47ac50 ORR	X17, XZR, X26

0x47ac54 CMP	X3, X17

0x47ac58 B.GE	47a5d8

0x47ac5c LDR	X7, [X0, #24]

0x47ac60 CMP	X7, #0

0x47ac64 CSEL	X19, X19, X0, #1

0x47ac68 CSEL	W16, W22, WZR, #1

0x47ac6c B	47aabc

0x47ac70 CMP	X3, X17

0x47ac74 B.GE	47a660

0x47ac78 ORR	X19, XZR, X21

0x47ac7c B	47a760

  (1347) 0x47ac80 CMP	X10, X11

  (1347) 0x47ac84 B.GE	47a7b4

  (1347) 0x47ac88 ORR	X19, XZR, X21

  (1347) 0x47ac8c CBNZ	X26, 47aab0

0x47ac90 B	47acec

0x47ac94 CMP	X5, X17

0x47ac98 B.GE	47a6e8

0x47ac9c ORR	X19, XZR, X21

0x47aca0 B	47ac18

0x47aca4 ORR	X13, XZR, X27

0x47aca8 CMP	X13, X0

0x47acac B.GE	47a894

0x47acb0 LDR	X16, [X19, #24]

0x47acb4 CMP	X16, #0

0x47acb8 CSEL	X26, X12, X19, #1

0x47acbc CSEL	W22, W22, WZR, #1

0x47acc0 B	47a950

0x47acc4 ORR	X10, XZR, X26

0x47acc8 CMP	X10, X9

0x47accc B.GE	47a55c

0x47acd0 LDR	X26, [X19, #24]

0x47acd4 CMP	X26, #0

0x47acd8 CSEL	X19, X0, X19, #1

0x47acdc CSEL	W16, W22, WZR, #1

0x47ace0 B	47aabc

  (1347) 0x47ace4 MOVZ	X19, #0

  (1347) 0x47ace8 B	47a50c

0x47acec MOVZ	X19, #0

0x47acf0 B	47a7b4

0x47acf4 HINT	#0

0x47acf8 HINT	#0

0x47acfc HINT	#0

Coverage (%)	Name	Source Location	Module
►14.29+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:204	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:189	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	qmcplusplus::ParticleSet::make[...]	ParticleSet.cpp:292	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:189	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:194	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:207	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►14.29+	qmcplusplus::ParticleSet::setA[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/usr/include/c++/11/bits/stl_tree.h:273,287,302-303,735,750,779-780,788,1902-1904,2066-2081,2172-2185,2193-2201,2331-2338,2435
/usr/include/c++/11/tuple:1771-1772
/usr/include/c++/11/bits/stl_map.h:499
/usr/include/c++/11/ext/new_allocator.h:121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-121

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.00 to 9.50 cycles (7.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 67.00 to 8.59 cycles (7.80x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.00 to 5.00 cycles (13.40x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 985 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	434
loop length	1736
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

53.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	67.00	67.00	45.25	45.25	45.25	45.25	0.00	0.00	0.00	0.00	40.67	40.67	40.67	4.00	4.00
cycles	67.00	67.00	45.25	45.25	45.25	45.25	0.00	0.00	0.00	0.00	40.67	40.67	40.67	4.00	4.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	53.25
Overall L1	67.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.00 cycles. At this rate:

15% of peak load performance is reached (14.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47a180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W22, 47a1a0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CMP X24, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a610 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CMP X19, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a69c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 47f160 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a3d4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X26, X18, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X26, X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X1, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a51c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47a5a8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B.NE 47a524 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 47a5a8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ab4c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47acc4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47acc8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ac20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47abc0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47abc8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 47ab88 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a564 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aab8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac50 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xad0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ab04 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x984>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aacc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aad4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X6, 47aa10 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a5e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7c4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X6, 47a730 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a66c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
LDR X10, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X8, 47a794 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a700 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W5, 47a9e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W7, 47aa54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a688 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W5, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a690 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a71c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W7, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a724 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47ac48 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X27, X1, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a850 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 47a8cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B.NE 47a858 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X17, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GT 47a8cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47abb8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aca4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aca8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47abdc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ab9c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aba4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X26, 47ab54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a89c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a934 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a938 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ab28 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aae8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x968>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aaf0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X9, 47aa7c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a904 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a8fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X26, X19, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W22, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W5, 47ab08 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aa30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X2, 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47ace4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W8, 47ab2c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aa9c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X26, 47acec <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W16, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a764 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a5fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W5, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a604 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a920 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W8, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a928 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa3c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47aa18 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x898>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aaa4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47aa84 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W18, 47abe0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ab74 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aaa4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W12, 47ac24 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47aa30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X14, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a8b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W18, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a8c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a580 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a588 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ab80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47ab5c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa3c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47ab90 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a450 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X17, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a5d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X19, X19, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a660 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47acec <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a6e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47ac18 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a894 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X26, X12, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W22, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a55c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X19, X0, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/usr/include/c++/11/bits/stl_tree.h:273,287,302-303,735,750,779-780,788,1902-1904,2066-2081,2172-2185,2193-2201,2331-2338,2435
/usr/include/c++/11/tuple:1771-1772
/usr/include/c++/11/bits/stl_map.h:499
/usr/include/c++/11/ext/new_allocator.h:121,139
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-121

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.00 to 9.50 cycles (7.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.00 to 5.00 cycles (13.40x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 985 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	434
loop length	1736
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

53.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	67.00	67.00	45.25	45.25	45.25	45.25	0.00	0.00	0.00	0.00	40.67	40.67	40.67	4.00	4.00
cycles	67.00	67.00	45.25	45.25	45.25	45.25	0.00	0.00	0.00	0.00	40.67	40.67	40.67	4.00	4.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	53.25
Overall L1	67.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.00 cycles. At this rate:

15% of peak load performance is reached (14.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47a180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W22, 47a1a0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CMP X24, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a610 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a4c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CMP X19, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a69c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x67c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 47f160 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE9pop_timerEPS3_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a3d4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X26, X18, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X26, X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X1, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a51c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47a5a8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B.NE 47a524 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 47a5a8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ab4c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47acc4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47acc8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ac20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47abc0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47abc8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X13, 47ab88 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a564 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aab8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac50 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xad0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ab04 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x984>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aacc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aad4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X6, 47aa10 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a5e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac70 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7c4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X6, 47a730 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a66c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ac94 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
LDR X10, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a7e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X8, 47a794 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a700 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W5, 47a9e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W7, 47aa54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a688 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W5, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a690 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a71c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W7, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a724 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47ac48 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403b10 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X27, X1, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X23, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X20, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, XZR, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a850 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 47a8cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B.NE 47a858 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X17, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GT 47a8cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47abb8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4039c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aca4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X12, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aca8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47abdc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ab9c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aba4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X26, 47ab54 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a89c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X20, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a934 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a938 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X19, 47ab28 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aae8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x968>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aaf0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X9, 47aa7c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a904 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a8fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X26, X19, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W22, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W5, 47ab08 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aa30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a508 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X2, 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47ace4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W8, 47ab2c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47aa9c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X26, 47acec <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W16, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a764 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X30, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a5fc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W5, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a604 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a920 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W8, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a928 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa3c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47aa18 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x898>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aaa4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47aa84 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W18, 47abe0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47ab74 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a848 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aaa4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W12, 47ac24 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa20 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47aa30 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X14, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a8b8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W18, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a8c0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a580 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a588 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47ab80 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47ab5c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x9dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47aa3c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x8bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403ba0 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47ab90 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47a450 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X17, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a5d8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X19, X19, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a660 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a760 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47acec <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a6e8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47ac18 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0xa98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a894 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X26, X12, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W22, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a950 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47a55c <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X19, X0, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W22, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47aabc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47a7b4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv+0x634>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.06	0.03
○Loop 1351 - stl_tree.h:779-1904 - exec	0.02	0.01
○Loop 1350 - stl_tree.h:779-1904 - exec	0.01	0
▼Loop 1348 - stl_tree.h:273-2435 - exec–	0	0
▼Loop 1347 - NewTimer.h:119-121 - exec–	0.02	0.01
○Loop 1349 - NewTimer.cpp:99-101 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code