OV - exec - Function qmcplusplus::TimerType<qmcplusplus::CPUClock>::start()

	Function: qmcplusplus::TimerType<qmcplusplus::CPUClock>::start()	Module: exec	Source: NewTimer.cpp:37-81 [...]	Coverage: 0.03%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 37 - 81

--------------------------------------------------------------------------------

37: void TimerType<CLOCK>::start()

38: {

39:   if (active)

[...]

53:     for (int level = omp_get_level(); level > 0; level--)

54:       if (omp_get_ancestor_thread_num(level) != 0)

55:         is_true_master = false;

56:     if (is_true_master)

57:     {

58:       if (manager)

59:       {

60:         // compute current_stack_key

61:         TimerType* parent = manager->current_timer();

62:         if (parent)

63:         {

64:           current_stack_key = parent->get_stack_key();

65:           current_stack_key.add_id(timer_id);

66:         }

67:         else

68:         {

69:           current_stack_key = StackKey();

70:           current_stack_key.add_id(timer_id);

71:         }

72:

73:         manager->push_timer(this);

74:       }

75:       start_time = CLOCK()();

[...]

81: }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h: 92 - 93

--------------------------------------------------------------------------------

92:     if (CurrentTimerStack.size() > 0)

93:       current = CurrentTimerStack.back();

/usr/include/c++/11/bits/stl_vector.h: 919 - 919

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h: 33 - 33

--------------------------------------------------------------------------------

33:     return omp_get_wtime();

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 90 - 99

--------------------------------------------------------------------------------

90:     short_buckets[level] = c1;

91:     if (level >= max_level - 1)

92:     {

93:       timer_max_level_exceeded = true;

94:     }

95:     else

96:     {

97:       level++;

98:     }

99:   }

0x479f20 STP	X29, X30, [SP, #976]!

0x479f24 ADD	X29, SP, #0

0x479f28 STP	X19, X20, [SP, #16]

0x479f2c LDRB	W19, [X0, #56]

0x479f30 CBNZ	W19, 479f40

0x479f34 LDP	X19, X20, [SP, #16]

0x479f38 LDP	X29, X30, [SP], #48

0x479f3c RET

0x479f40 STP	X21, X22, [SP, #32]

0x479f44 ORR	X21, XZR, X0

0x479f48 BL	403a30

0x479f4c ORR	W20, WZR, W0

0x479f50 CMP	W0, #0

0x479f54 B.LE	47a0cc

0x479f58 ANDS	W1, W0, #128

0x479f5c SUB	W2, W0, #1

0x479f60 B.EQ	47a010

0x479f64 CMP	W1, #1

0x479f68 B.EQ	479ff8

0x479f6c CMP	W1, #2

0x479f70 B.EQ	479fe4

0x479f74 CMP	W1, #3

0x479f78 B.EQ	479fd0

0x479f7c CMP	W1, #4

0x479f80 B.EQ	479fbc

0x479f84 CMP	W1, #5

0x479f88 B.EQ	479fa8

0x479f8c CMP	W1, #6

0x479f90 B.NE	47a134

(1345) 0x479f94 ORR	W0, WZR, W20

(1345) 0x479f98 SUB	W20, W20, #1

(1345) 0x479f9c BL	403a50

(1345) 0x479fa0 CMP	W0, #0

(1345) 0x479fa4 CSEL	W19, W19, WZR, #0

(1345) 0x479fa8 ORR	W0, WZR, W20

(1345) 0x479fac SUB	W20, W20, #1

(1345) 0x479fb0 BL	403a50

(1345) 0x479fb4 CMP	W0, #0

(1345) 0x479fb8 CSEL	W19, W19, WZR, #0

(1345) 0x479fbc ORR	W0, WZR, W20

(1345) 0x479fc0 SUB	W20, W20, #1

(1345) 0x479fc4 BL	403a50

(1345) 0x479fc8 CMP	W0, #0

(1345) 0x479fcc CSEL	W19, W19, WZR, #0

(1345) 0x479fd0 ORR	W0, WZR, W20

(1345) 0x479fd4 SUB	W20, W20, #1

(1345) 0x479fd8 BL	403a50

(1345) 0x479fdc CMP	W0, #0

(1345) 0x479fe0 CSEL	W19, W19, WZR, #0

(1345) 0x479fe4 ORR	W0, WZR, W20

(1345) 0x479fe8 SUB	W20, W20, #1

(1345) 0x479fec BL	403a50

(1345) 0x479ff0 CMP	W0, #0

(1345) 0x479ff4 CSEL	W19, W19, WZR, #0

(1345) 0x479ff8 ORR	W0, WZR, W20

(1345) 0x479ffc BL	403a50

(1345) 0x47a000 CMP	W0, #0

(1345) 0x47a004 CSEL	W19, W19, WZR, #0

(1345) 0x47a008 SUBS	W20, W20, #1

(1345) 0x47a00c B.EQ	47a0b8

  (1346) 0x47a010 ORR	W0, WZR, W20

  (1346) 0x47a014 SUB	W22, W20, #1

  (1346) 0x47a018 BL	403a50

  (1346) 0x47a01c ORR	W3, WZR, W0

  (1346) 0x47a020 ORR	W0, WZR, W22

  (1346) 0x47a024 CMP	W3, #0

  (1346) 0x47a028 CSEL	W19, W19, WZR, #0

  (1346) 0x47a02c BL	403a50

  (1346) 0x47a030 ORR	W4, WZR, W0

  (1346) 0x47a034 SUB	W0, W22, #1

  (1346) 0x47a038 CMP	W4, #0

  (1346) 0x47a03c CSEL	W22, W19, WZR, #0

  (1346) 0x47a040 BL	403a50

  (1346) 0x47a044 ORR	W5, WZR, W0

  (1346) 0x47a048 SUB	W0, W20, #3

  (1346) 0x47a04c CMP	W5, #0

  (1346) 0x47a050 CSEL	W19, W22, WZR, #0

  (1346) 0x47a054 BL	403a50

  (1346) 0x47a058 ORR	W6, WZR, W0

  (1346) 0x47a05c SUB	W0, W20, #4

  (1346) 0x47a060 CMP	W6, #0

  (1346) 0x47a064 CSEL	W22, W19, WZR, #0

  (1346) 0x47a068 BL	403a50

  (1346) 0x47a06c ORR	W7, WZR, W0

  (1346) 0x47a070 SUB	W0, W20, #5

  (1346) 0x47a074 CMP	W7, #0

  (1346) 0x47a078 CSEL	W19, W22, WZR, #0

  (1346) 0x47a07c BL	403a50

  (1346) 0x47a080 ORR	W8, WZR, W0

  (1346) 0x47a084 SUB	W0, W20, #6

  (1346) 0x47a088 CMP	W8, #0

  (1346) 0x47a08c CSEL	W22, W19, WZR, #0

  (1346) 0x47a090 BL	403a50

  (1346) 0x47a094 ORR	W9, WZR, W0

  (1346) 0x47a098 SUB	W0, W20, #7

  (1346) 0x47a09c CMP	W9, #0

  (1346) 0x47a0a0 CSEL	W19, W22, WZR, #0

  (1346) 0x47a0a4 BL	403a50

  (1346) 0x47a0a8 CMP	W0, #0

  (1346) 0x47a0ac CSEL	W19, W19, WZR, #0

  (1346) 0x47a0b0 SUBS	W20, W20, #8

  (1346) 0x47a0b4 B.NE	47a010

(1345) 0x47a0b8 CBNZ	W19, 47a0cc

0x47a0bc LDP	X19, X20, [SP, #16]

0x47a0c0 LDP	X21, X22, [SP, #32]

0x47a0c4 LDP	X29, X30, [SP], #48

0x47a0c8 RET

(1345) 0x47a0cc LDR	X0, [X21, #72]

(1345) 0x47a0d0 CBZ	X0, 47a11c

0x47a0d4 LDP	X11, X12, [X0, #72]

0x47a0d8 LDRB	W10, [X21, #64]

0x47a0dc CMP	X11, X12

0x47a0e0 B.EQ	47a158

0x47a0e4 LDUR	X13, [X12, #504]

0x47a0e8 CBZ	X13, 47a158

0x47a0ec LDP	X16, X17, [X13, #80]

0x47a0f0 ADD	X15, X21, #80

0x47a0f4 STP	X16, X17, [X21, #80]

0x47a0f8 LDR	W17, [X13, #96]

0x47a0fc STR	W17, [X15, #16]

0x47a100 STRB	W10, [X15, X17,SXTW]

0x47a104 CMP	W17, #14

0x47a108 B.GT	47a148

0x47a10c ADD	W18, W17, #1

0x47a110 STR	W18, [X15, #16]

0x47a114 ORR	X1, XZR, X21

0x47a118 BL	47ef40

(1345) 0x47a11c BL	403820

(1345) 0x47a120 STR	D0, [X21]

(1345) 0x47a124 LDP	X19, X20, [SP, #16]

(1345) 0x47a128 LDP	X21, X22, [SP, #32]

(1345) 0x47a12c LDP	X29, X30, [SP], #48

(1345) 0x47a130 RET

(1345) 0x47a134 ORR	W20, WZR, W2

(1345) 0x47a138 BL	403a50

(1345) 0x47a13c CMP	W0, #0

(1345) 0x47a140 CSEL	W19, W19, WZR, #0

(1345) 0x47a144 B	479f94

0x47a148 ADRP	X30,

0x47a14c MOVZ	W1, #1

0x47a150 STRB	W1, [X30, #1360]

0x47a154 B	47a114

0x47a158 MOVZ	W14, #1

0x47a15c STP	XZR, XZR, [X21, #80]

0x47a160 STRB	W10, [X21, #80]

0x47a164 STR	W14, [X21, #96]

0x47a168 B	47a114

0x47a16c HINT	#0

0x47a170 HINT	#0

0x47a174 HINT	#0

0x47a178 HINT	#0

0x47a17c HINT	#0

Coverage (%)	Name	Source Location	Module
►25.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:199	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	qmcplusplus::WaveFunction::acc[...]	stl_vector.h:1043	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:1043	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:199	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:37-81
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:37-39,53-75,81
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/usr/include/c++/11/bits/stl_vector.h:919
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-99

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 1.12 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 126 bytes. The binary function is storing 95 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	5.50	5.50
cycles	9.00	9.00	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	5.50	5.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

14% of peak load performance is reached (14.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 479f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W19, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W19, 479f40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a30 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47a0cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W2, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47a010 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479ff8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fe4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fd0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fbc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fa8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a134 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDRB W10, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a158 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X13, 47a158 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [X13, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X15, X21, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, X17, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W17, [X13, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W17, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W10, [X15, X17,SXTW]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W17, #14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 47a148 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47ef40 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE10push_timerEPS3_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X30, <4c2148>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W1, [X30, #1360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a114 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, XZR, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W10, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W14, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a114 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:37-81
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:37-39,53-75,81
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/usr/include/c++/11/bits/stl_vector.h:919
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/Clock.h:33
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-99

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 126 bytes. The binary function is storing 95 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	5.50	5.50
cycles	9.00	9.00	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	5.50	5.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

14% of peak load performance is reached (14.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 479f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRB W19, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W19, 479f40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a30 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47a0cc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W1, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W2, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 47a010 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479ff8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fe4 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fd0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fbc <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 479fa8 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47a134 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDRB W10, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47a158 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X12, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X13, 47a158 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [X13, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X15, X21, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, X17, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W17, [X13, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W17, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W10, [X15, X17,SXTW]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W17, #14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 47a148 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47ef40 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINS_8CPUClockEEEE10push_timerEPS3_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X30, <4c2148>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W1, [X30, #1360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a114 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, XZR, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W10, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W14, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47a114 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::start()–	0.03	0.02
▼Loop 1345 - NewTimer.cpp:53-81 - exec–	0.02	0.01
○Loop 1346 - NewTimer.cpp:53-55 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code