OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::resize(int, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::resize ...	Module: exec	Source: DiracDeterminantRef.cpp:61-79 [...]	Coverage: 0.04%

/usr/include/c++/11/bits/stl_uninitialized.h: 1009 - 1011

--------------------------------------------------------------------------------

1009:       ptrdiff_t __count = __last - __first;

1010:       if (__count > 0)

1011: 	__builtin_memmove(__result, __first, __count * sizeof(_Tp));

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 61 - 79

--------------------------------------------------------------------------------

61: void DiracDeterminantRef<DU_TYPE>::resize(int nel, int morb)

62: {

63:   int norb = morb;

64:   if (norb <= 0)

65:     norb = nel; // for morb == -1 (default)

66:   updateEng.resize(norb, ndelay);

67:   psiM.resize(nel, norb);

[...]

73:   LastIndex   = FirstIndex + nel;

74:   NumPtcls    = nel;

75:   NumOrbitals = norb;

76:

77:   dpsiV.resize(NumOrbitals);

78:   d2psiV.resize(NumOrbitals);

79: }

/usr/include/c++/11/bits/stl_construct.h: 108 - 108

--------------------------------------------------------------------------------

108:     _Construct(_Tp* __p, _Args&&... __args)

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 101 - 103

--------------------------------------------------------------------------------

101:     D1      = n;

102:     D2      = m;

103:     TotSize = n * m;

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/usr/include/c++/11/bits/stl_algobase.h: 911 - 1120

--------------------------------------------------------------------------------

911:       for (; __first != __last; ++__first)

[...]

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

[...]

1115:       if (__n <= 0)

1116: 	return __first;

1117:

1118:       __glibcxx_requires_can_increment(__first, __n);

1119:

1120:       std::__fill_a(__first, __first + __n, __value);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 185 - 302

--------------------------------------------------------------------------------

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

/usr/include/c++/11/bits/alloc_traits.h: 492 - 492

--------------------------------------------------------------------------------

492:       { __a.deallocate(__p, __n); }

/usr/include/c++/11/bits/stl_vector.h: 346 - 1798

--------------------------------------------------------------------------------

346: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

353: 	if (__p)

[...]

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

939: 	if (__new_size > size())

940: 	  _M_default_append(__new_size - size());

941: 	else if (__new_size < size())

942: 	  _M_erase_at_end(this->_M_impl._M_start + __new_size);

[...]

1758: 	if (max_size() - size() < __n)

1759: 	  __throw_length_error(__N(__s));

[...]

1794: 	if (size_type __n = this->_M_impl._M_finish - __pos)

1795: 	  {

1796: 	    std::_Destroy(__pos, this->_M_impl._M_finish,

1797: 			  _M_get_Tp_allocator());

1798: 	    this->_M_impl._M_finish = __pos;

/usr/include/c++/11/ext/new_allocator.h: 105 - 139

--------------------------------------------------------------------------------

105: 	if (__builtin_expect(__n > this->_M_max_size(), false))

106: 	  {

107: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

108: 	    // 3190. allocator::allocate sometimes returns too little storage

109: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

110: 	      std::__throw_bad_array_new_length();

111: 	    std::__throw_bad_alloc();

[...]

121: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

139: 	::operator delete(__p

/usr/include/c++/11/bits/vector.tcc: 618 - 680

--------------------------------------------------------------------------------

618: 					 - this->_M_impl._M_finish);

619:

620: 	  if (__size > max_size() || __navail > max_size() - __size)

621: 	    __builtin_unreachable();

622:

623: 	  if (__navail >= __n)

[...]

640: 		      std::__uninitialized_default_n_a(__new_start + __size,

[...]

648: 		  _S_relocate(this->_M_impl._M_start, this->_M_impl._M_finish,

[...]

677: 			    - this->_M_impl._M_start);

678: 	      this->_M_impl._M_start = __new_start;

679: 	      this->_M_impl._M_finish = __new_start + __size + __n;

680: 	      this->_M_impl._M_end_of_storage = __new_start + __len;

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 62 - 62

--------------------------------------------------------------------------------

62:     V.resize(delay, norb);

0x44f520 STP	X29, X30, [SP, #912]!

0x44f524 ADD	X29, SP, #0

0x44f528 CMP	W2, #0

0x44f52c STP	X25, X26, [SP, #64]

0x44f530 LDR	W26, [X0, #1160]

0x44f534 STP	X27, X28, [SP, #80]

0x44f538 ADD	X27, X0, #608

0x44f53c STP	X19, X20, [SP, #16]

0x44f540 ORR	X19, XZR, X0

0x44f544 STP	X23, X24, [SP, #48]

0x44f548 CSEL	W23, W2, W1, #12

0x44f54c ORR	W24, WZR, W1

0x44f550 SBFM	X20, X23, #0, #31

0x44f554 LDP	X0, X1, [X27, #8]

0x44f558 STP	X21, X22, [SP, #32]

0x44f55c SMADDL	X21, W26, W23, XZR

0x44f560 SBFM	X22, X26, #0, #31

0x44f564 STR	X22, [X19, #584]

0x44f568 STR	X20, [X19, #592]

0x44f56c STR	X21, [X19, #600]

0x44f570 CMP	X0, X1

0x44f574 B.HI	4503f0

0x44f578 ORR	X25, XZR, X20

0x44f57c CMP	X21, X1

0x44f580 B.HI	44fbe8

0x44f584 CMP	X21, X0

0x44f588 B.HI	44f98c

(909) 0x44f58c STR	X21, [X27, #8]

    (907) 0x44f590 ADD	X27, X19, #544

    (907) 0x44f594 LDP	X5, X6, [X27, #8]

    (907) 0x44f598 STR	X22, [X19, #520]

    (907) 0x44f59c STR	X20, [X19, #528]

    (907) 0x44f5a0 STR	X21, [X19, #536]

    (907) 0x44f5a4 CMP	X5, X6

    (907) 0x44f5a8 B.HI	4503cc

    (907) 0x44f5ac CMP	X21, X6

    (907) 0x44f5b0 B.HI	44fc20

    (907) 0x44f5b4 CMP	X21, X5

    (907) 0x44f5b8 B.HI	44f9ac

    (907) 0x44f5bc STR	X21, [X27, #8]

    (907) 0x44f5c0 ADD	X27, X19, #816

    (907) 0x44f5c4 LDP	X10, X11, [X27, #8]

    (907) 0x44f5c8 CMP	X10, X11

    (907) 0x44f5cc B.HI	450378

    (907) 0x44f5d0 CMP	X22, X11

    (907) 0x44f5d4 B.HI	44fc58

    (907) 0x44f5d8 CMP	X22, X10

    (907) 0x44f5dc B.HI	44f9cc

    (907) 0x44f5e0 STR	X22, [X27, #8]

    (907) 0x44f5e4 ADD	X27, X19, #776

    (907) 0x44f5e8 LDP	X15, X16, [X27, #8]

    (907) 0x44f5ec CMP	X15, X16

    (907) 0x44f5f0 B.HI	4503b0

    (907) 0x44f5f4 CMP	X20, X16

    (907) 0x44f5f8 B.HI	44fc90

    (907) 0x44f5fc CMP	X20, X15

    (907) 0x44f600 B.HI	44f9ec

    (907) 0x44f604 STR	X20, [X27, #8]

    (907) 0x44f608 ADD	X27, X19, #736

    (907) 0x44f60c LDP	X0, X1, [X27, #8]

    (907) 0x44f610 STR	X20, [X19, #712]

    (907) 0x44f614 STR	X22, [X19, #720]

    (907) 0x44f618 STR	X21, [X19, #728]

    (907) 0x44f61c CMP	X0, X1

    (907) 0x44f620 B.HI	4504cc

    (907) 0x44f624 CMP	X21, X1

    (907) 0x44f628 B.HI	44fcc8

    (907) 0x44f62c CMP	X21, X0

    (907) 0x44f630 B.HI	44fa0c

    (907) 0x44f634 STR	X21, [X27, #8]

    (907) 0x44f638 ADD	X27, X19, #672

    (907) 0x44f63c SMADDL	X21, W26, W26, XZR

    (907) 0x44f640 LDP	X26, X5, [X27, #8]

    (907) 0x44f644 STR	X22, [X19, #648]

    (907) 0x44f648 STR	X22, [X19, #656]

    (907) 0x44f64c STR	X21, [X19, #664]

    (907) 0x44f650 CMP	X26, X5

    (907) 0x44f654 B.HI	450348

    (907) 0x44f658 CMP	X5, X21

    (907) 0x44f65c B.CC	44fd00

    (907) 0x44f660 CMP	X26, X21

    (907) 0x44f664 B.CC	44fa2c

    (907) 0x44f668 STR	X21, [X27, #8]

    (907) 0x44f66c LDR	X21, [X19, #856]

    (907) 0x44f670 ADD	X26, X19, #856

    (907) 0x44f674 LDR	X9, [X26, #8]

    (907) 0x44f678 SUB	X1, X9, X21

    (907) 0x44f67c SBFM	X10, X1, #2, #63

    (907) 0x44f680 CMP	X22, X10

    (907) 0x44f684 B.HI	44fd50

    (907) 0x44f688 B.CC	44fa4c

    (907) 0x44f68c ADD	X26, X19, #232

    (907) 0x44f690 SMADDL	X21, W24, W23, XZR

    (907) 0x44f694 SBFM	X28, X24, #0, #31

    (907) 0x44f698 LDP	X9, X10, [X26, #8]

    (907) 0x44f69c STP	X28, X20, [X19, #208]

    (907) 0x44f6a0 STR	X21, [X19, #224]

    (907) 0x44f6a4 CMP	X9, X10

    (907) 0x44f6a8 B.HI	45048c

    (907) 0x44f6ac CMP	X21, X10

    (907) 0x44f6b0 B.HI	44fdd8

    (907) 0x44f6b4 CMP	X21, X9

    (907) 0x44f6b8 B.HI	44fa60

    (907) 0x44f6bc STR	X21, [X26, #8]

    (907) 0x44f6c0 ADD	X26, X19, #296

    (907) 0x44f6c4 LDP	X13, X14, [X26, #8]

    (907) 0x44f6c8 STP	X28, X20, [X19, #272]

    (907) 0x44f6cc STR	X21, [X19, #288]

    (907) 0x44f6d0 CMP	X13, X14

    (907) 0x44f6d4 B.HI	450470

    (907) 0x44f6d8 CMP	X21, X14

    (907) 0x44f6dc B.HI	44fe10

    (907) 0x44f6e0 CMP	X21, X13

    (907) 0x44f6e4 B.HI	44fa80

    (907) 0x44f6e8 STR	X21, [X26, #8]

    (907) 0x44f6ec ADD	X22, X19, #360

    (907) 0x44f6f0 LDP	X30, X1, [X22, #8]

    (907) 0x44f6f4 STP	X28, X20, [X19, #336]

    (907) 0x44f6f8 STR	X21, [X19, #352]

    (907) 0x44f6fc CMP	X30, X1

    (907) 0x44f700 B.HI	4504b0

    (907) 0x44f704 CMP	X21, X1

    (907) 0x44f708 B.HI	44ff38

    (907) 0x44f70c CMP	X21, X30

    (907) 0x44f710 B.HI	44fb90

    (907) 0x44f714 STR	X21, [X22, #8]

    (907) 0x44f718 ADD	X26, X19, #400

    (907) 0x44f71c LDP	X5, X6, [X26, #8]

    (907) 0x44f720 CMP	X5, X6

    (907) 0x44f724 B.HI	4504f0

    (907) 0x44f728 CMP	X6, X20

    (907) 0x44f72c B.CC	44fbb0

    (907) 0x44f730 CMP	X5, X20

    (907) 0x44f734 B.CS	44f754

    (907) 0x44f738 LDR	X0, [X26, #24]

    (907) 0x44f73c SUB	X7, X20, X5

    (907) 0x44f740 UBFM	X2, X7, #61, #60

    (907) 0x44f744 ADD	X0, X0, X5,LSL #3

    (907) 0x44f748 CBZ	X2, 44f754

0x44f74c MOVZ	W1, #0

0x44f750 BL	403890

    (907) 0x44f754 STR	X20, [X26, #8]

    (907) 0x44f758 ADD	X26, X19, #1032

    (907) 0x44f75c LDP	X9, X10, [X26, #8]

    (907) 0x44f760 CMP	X9, X10

    (907) 0x44f764 B.HI	450430

    (907) 0x44f768 CMP	X10, X20

    (907) 0x44f76c B.CC	44ff70

    (907) 0x44f770 CMP	X9, X20

    (907) 0x44f774 B.CS	44f794

    (907) 0x44f778 LDR	X12, [X26, #24]

    (907) 0x44f77c SUB	X11, X20, X9

    (907) 0x44f780 UBFM	X2, X11, #61, #60

    (907) 0x44f784 ADD	X0, X12, X9,LSL #3

    (907) 0x44f788 CBZ	X2, 44f794

0x44f78c MOVZ	W1, #0

0x44f790 BL	403890

    (907) 0x44f794 STR	X20, [X26, #8]

    (907) 0x44f798 ADD	X26, X19, #168

    (907) 0x44f79c LDP	X14, X15, [X26, #8]

    (907) 0x44f7a0 STP	X28, X20, [X19, #144]

    (907) 0x44f7a4 STR	X21, [X19, #160]

    (907) 0x44f7a8 CMP	X14, X15

    (907) 0x44f7ac B.HI	45044c

    (907) 0x44f7b0 CMP	X21, X15

    (907) 0x44f7b4 B.HI	44ffa8

(909) 0x44f7b8 CMP	X21, X14

(909) 0x44f7bc B.LS	44f7dc

(909) 0x44f7c0 LDR	X16, [X26, #24]

(909) 0x44f7c4 SUB	X28, X21, X14

(909) 0x44f7c8 UBFM	X2, X28, #61, #60

(909) 0x44f7cc ADD	X0, X16, X14,LSL #3

(909) 0x44f7d0 CBZ	X2, 44f7dc

0x44f7d4 MOVZ	W1, #0

0x44f7d8 BL	403890

(909) 0x44f7dc STR	X21, [X26, #8]

(909) 0x44f7e0 LDR	W18, [X19, #1144]

(909) 0x44f7e4 ADD	X21, X19, #440

(909) 0x44f7e8 LDP	X1, X3, [X21, #8]

(909) 0x44f7ec STR	W23, [X19, #1152]

(909) 0x44f7f0 ADD	W30, W18, W24

(909) 0x44f7f4 STR	W24, [X19, #1156]

(909) 0x44f7f8 STR	W30, [X19, #1148]

(909) 0x44f7fc CMP	X1, X3

(909) 0x44f800 B.HI	45040c

(909) 0x44f804 CMP	X20, X3

(909) 0x44f808 B.HI	44ffe0

(909) 0x44f80c CMP	X20, X1

(909) 0x44f810 B.LS	44f92c

(909) 0x44f814 LDR	X2, [X21, #24]

(909) 0x44f818 ADD	X24, X1, X1,LSL #1

(909) 0x44f81c SUB	X23, X20, X1

(909) 0x44f820 ADD	X4, X23, X23,LSL #1

(909) 0x44f824 ADD	X0, X2, X24,LSL #3

(909) 0x44f828 ADD	X5, X0, X4,LSL #3

(909) 0x44f82c CMP	X0, X5

(909) 0x44f830 B.EQ	44f92c

(909) 0x44f834 MOVZ	X7, #43691

(909) 0x44f838 SUB	X6, X5, X0

(909) 0x44f83c MOVK	X7, #43690

(909) 0x44f840 SUB	X8, X6, #24

(909) 0x44f844 MOVK	X7, #43690

(909) 0x44f848 UBFM	X9, X8, #3, #63

(909) 0x44f84c MOVK	X7, #2730

(909) 0x44f850 MADD	X10, X9, X7, XZR

(909) 0x44f854 ADD	X11, X10, #1

(909) 0x44f858 ANDS	X12, X11, #4224

(909) 0x44f85c B.EQ	44f8ec

(909) 0x44f860 CMP	X12, #1

(909) 0x44f864 B.EQ	44f8d8

(909) 0x44f868 CMP	X12, #2

(909) 0x44f86c B.EQ	44f8cc

(909) 0x44f870 CMP	X12, #3

(909) 0x44f874 B.EQ	44f8c0

(909) 0x44f878 CMP	X12, #4

(909) 0x44f87c B.EQ	44f8b4

(909) 0x44f880 CMP	X12, #5

(909) 0x44f884 B.EQ	44f8a8

(909) 0x44f888 CMP	X12, #6

(909) 0x44f88c B.EQ	44f89c

(909) 0x44f890 STP	XZR, XZR, [X0]

(909) 0x44f894 ADD	X0, X0, #24

(909) 0x44f898 STUR	XZR, [X0, #504]

(909) 0x44f89c STP	XZR, XZR, [X0]

(909) 0x44f8a0 ADD	X0, X0, #24

(909) 0x44f8a4 STUR	XZR, [X0, #504]

(909) 0x44f8a8 STP	XZR, XZR, [X0]

(909) 0x44f8ac ADD	X0, X0, #24

(909) 0x44f8b0 STUR	XZR, [X0, #504]

(909) 0x44f8b4 STP	XZR, XZR, [X0]

(909) 0x44f8b8 ADD	X0, X0, #24

(909) 0x44f8bc STUR	XZR, [X0, #504]

(909) 0x44f8c0 STP	XZR, XZR, [X0]

(909) 0x44f8c4 ADD	X0, X0, #24

(909) 0x44f8c8 STUR	XZR, [X0, #504]

(909) 0x44f8cc STP	XZR, XZR, [X0]

(909) 0x44f8d0 ADD	X0, X0, #24

(909) 0x44f8d4 STUR	XZR, [X0, #504]

(909) 0x44f8d8 STP	XZR, XZR, [X0]

(909) 0x44f8dc ADD	X0, X0, #24

(909) 0x44f8e0 STUR	XZR, [X0, #504]

(909) 0x44f8e4 CMP	X5, X0

(909) 0x44f8e8 B.EQ	44f92c

  (913) 0x44f8ec ADD	X13, X0, #168

  (913) 0x44f8f0 STP	XZR, XZR, [X0]

  (913) 0x44f8f4 STP	XZR, XZR, [X0, #16]

  (913) 0x44f8f8 STP	XZR, XZR, [X0, #32]

  (913) 0x44f8fc STP	XZR, XZR, [X0, #48]

  (913) 0x44f900 STP	XZR, XZR, [X0, #64]

  (913) 0x44f904 STP	XZR, XZR, [X0, #80]

  (913) 0x44f908 STP	XZR, XZR, [X0, #96]

  (913) 0x44f90c STP	XZR, XZR, [X0, #112]

  (913) 0x44f910 STP	XZR, XZR, [X0, #128]

  (913) 0x44f914 STP	XZR, XZR, [X0, #144]

  (913) 0x44f918 STP	XZR, XZR, [X0, #160]

  (913) 0x44f91c ADD	X0, X0, #192

  (913) 0x44f920 STP	XZR, XZR, [X13, #8]

  (913) 0x44f924 CMP	X5, X0

  (913) 0x44f928 B.NE	44f8ec

(909) 0x44f92c STR	X20, [X21, #8]

(909) 0x44f930 ADD	X19, X19, #480

(909) 0x44f934 LDP	X3, X1, [X19, #8]

(909) 0x44f938 CMP	X3, X1

(909) 0x44f93c B.HI	45050c

(909) 0x44f940 CMP	X25, X1

(909) 0x44f944 B.HI	450118

(909) 0x44f948 CMP	X25, X3

(909) 0x44f94c B.LS	44f96c

(909) 0x44f950 LDR	X23, [X19, #24]

(909) 0x44f954 SUB	X24, X25, X3

(909) 0x44f958 UBFM	X2, X24, #61, #60

(909) 0x44f95c ADD	X0, X23, X3,LSL #3

(909) 0x44f960 CBZ	X2, 44f96c

0x44f964 MOVZ	W1, #0

0x44f968 BL	403890

(909) 0x44f96c STR	X25, [X19, #8]

(909) 0x44f970 LDP	X19, X20, [SP, #16]

(909) 0x44f974 LDP	X21, X22, [SP, #32]

(909) 0x44f978 LDP	X23, X24, [SP, #48]

(909) 0x44f97c LDP	X25, X26, [SP, #64]

(909) 0x44f980 LDP	X27, X28, [SP, #80]

(909) 0x44f984 LDP	X29, X30, [SP], #112

(909) 0x44f988 RET

(909) 0x44f98c LDR	X3, [X27, #24]

(909) 0x44f990 SUB	X2, X21, X0

(909) 0x44f994 UBFM	X2, X2, #61, #60

(909) 0x44f998 ADD	X0, X3, X0,LSL #3

(909) 0x44f99c CBZ	X2, 44f58c

0x44f9a0 MOVZ	W1, #0

0x44f9a4 BL	403890

0x44f9a8 B	44f58c

    (907) 0x44f9ac LDR	X8, [X27, #24]

    (907) 0x44f9b0 SUB	X7, X21, X5

    (907) 0x44f9b4 UBFM	X2, X7, #61, #60

    (907) 0x44f9b8 ADD	X0, X8, X5,LSL #3

    (907) 0x44f9bc CBZ	X2, 44f5bc

0x44f9c0 MOVZ	W1, #0

0x44f9c4 BL	403890

0x44f9c8 B	44f5bc

    (907) 0x44f9cc LDR	X13, [X27, #24]

    (907) 0x44f9d0 SUB	X12, X22, X10

    (907) 0x44f9d4 UBFM	X2, X12, #61, #60

    (907) 0x44f9d8 ADD	X0, X13, X10,LSL #3

    (907) 0x44f9dc CBZ	X2, 44f5e0

0x44f9e0 MOVZ	W1, #0

0x44f9e4 BL	403890

0x44f9e8 B	44f5e0

    (907) 0x44f9ec LDR	X18, [X27, #24]

    (907) 0x44f9f0 SUB	X17, X20, X15

    (907) 0x44f9f4 UBFM	X2, X17, #61, #60

    (907) 0x44f9f8 ADD	X0, X18, X15,LSL #3

    (907) 0x44f9fc CBZ	X2, 44f604

0x44fa00 MOVZ	W1, #0

0x44fa04 BL	403890

0x44fa08 B	44f604

    (907) 0x44fa0c LDR	X3, [X27, #24]

    (907) 0x44fa10 SUB	X2, X21, X0

    (907) 0x44fa14 UBFM	X2, X2, #61, #60

    (907) 0x44fa18 ADD	X0, X3, X0,LSL #3

    (907) 0x44fa1c CBZ	X2, 44f634

0x44fa20 MOVZ	W1, #0

0x44fa24 BL	403890

0x44fa28 B	44f634

    (907) 0x44fa2c LDR	X7, [X27, #24]

    (907) 0x44fa30 SUB	X6, X21, X26

    (907) 0x44fa34 UBFM	X2, X6, #61, #60

    (907) 0x44fa38 ADD	X0, X7, X26,LSL #3

    (907) 0x44fa3c CBZ	X2, 44f668

0x44fa40 MOVZ	W1, #0

0x44fa44 BL	403890

0x44fa48 B	44f668

    (907) 0x44fa4c ADD	X21, X21, X22,LSL #2

    (907) 0x44fa50 CMP	X9, X21

    (907) 0x44fa54 B.EQ	44f68c

    (907) 0x44fa58 STR	X21, [X26, #8]

    (907) 0x44fa5c B	44f68c

    (907) 0x44fa60 LDR	X27, [X26, #24]

    (907) 0x44fa64 SUB	X11, X21, X9

    (907) 0x44fa68 UBFM	X2, X11, #61, #60

    (907) 0x44fa6c ADD	X0, X27, X9,LSL #3

    (907) 0x44fa70 CBZ	X2, 44f6bc

0x44fa74 MOVZ	W1, #0

0x44fa78 BL	403890

0x44fa7c B	44f6bc

    (907) 0x44fa80 LDR	X18, [X26, #24]

    (907) 0x44fa84 ADD	X15, X13, X13,LSL #1

    (907) 0x44fa88 SUB	X16, X21, X13

    (907) 0x44fa8c ADD	X17, X16, X16,LSL #1

    (907) 0x44fa90 ADD	X0, X18, X15,LSL #3

    (907) 0x44fa94 ADD	X1, X0, X17,LSL #3

    (907) 0x44fa98 CMP	X0, X1

    (907) 0x44fa9c B.EQ	44f6e8

    (907) 0x44faa0 MOVZ	X3, #43691

    (907) 0x44faa4 SUB	X30, X1, X0

    (907) 0x44faa8 MOVK	X3, #43690

    (907) 0x44faac SUB	X4, X30, #24

    (907) 0x44fab0 MOVK	X3, #43690

    (907) 0x44fab4 UBFM	X2, X4, #3, #63

    (907) 0x44fab8 MOVK	X3, #2730

    (907) 0x44fabc MADD	X5, X2, X3, XZR

    (907) 0x44fac0 ADD	X6, X5, #1

    (907) 0x44fac4 ANDS	X7, X6, #4224

    (907) 0x44fac8 B.EQ	44fb4c

    (907) 0x44facc CMP	X7, #1

    (907) 0x44fad0 B.EQ	44fb38

    (907) 0x44fad4 CMP	X7, #2

    (907) 0x44fad8 B.EQ	44fb2c

    (907) 0x44fadc CMP	X7, #3

    (907) 0x44fae0 B.EQ	44fb20

    (907) 0x44fae4 CMP	X7, #4

    (907) 0x44fae8 B.EQ	44fb14

    (907) 0x44faec CMP	X7, #5

    (907) 0x44faf0 B.EQ	44fb08

    (907) 0x44faf4 CMP	X7, #6

    (907) 0x44faf8 B.NE	4502d4

    (907) 0x44fafc STP	XZR, XZR, [X0]

    (907) 0x44fb00 ADD	X0, X0, #24

    (907) 0x44fb04 STUR	XZR, [X0, #504]

    (907) 0x44fb08 STP	XZR, XZR, [X0]

    (907) 0x44fb0c ADD	X0, X0, #24

    (907) 0x44fb10 STUR	XZR, [X0, #504]

    (907) 0x44fb14 STP	XZR, XZR, [X0]

    (907) 0x44fb18 ADD	X0, X0, #24

    (907) 0x44fb1c STUR	XZR, [X0, #504]

    (907) 0x44fb20 STP	XZR, XZR, [X0]

    (907) 0x44fb24 ADD	X0, X0, #24

    (907) 0x44fb28 STUR	XZR, [X0, #504]

    (907) 0x44fb2c STP	XZR, XZR, [X0]

    (907) 0x44fb30 ADD	X0, X0, #24

    (907) 0x44fb34 STUR	XZR, [X0, #504]

    (907) 0x44fb38 STP	XZR, XZR, [X0]

    (907) 0x44fb3c ADD	X0, X0, #24

    (907) 0x44fb40 STUR	XZR, [X0, #504]

    (907) 0x44fb44 CMP	X1, X0

    (907) 0x44fb48 B.EQ	44f6e8

      (911) 0x44fb4c ADD	X8, X0, #168

      (911) 0x44fb50 STP	XZR, XZR, [X0]

      (911) 0x44fb54 STP	XZR, XZR, [X0, #16]

      (911) 0x44fb58 STP	XZR, XZR, [X0, #32]

      (911) 0x44fb5c STP	XZR, XZR, [X0, #48]

      (911) 0x44fb60 STP	XZR, XZR, [X0, #64]

      (911) 0x44fb64 STP	XZR, XZR, [X0, #80]

      (911) 0x44fb68 STP	XZR, XZR, [X0, #96]

      (911) 0x44fb6c STP	XZR, XZR, [X0, #112]

      (911) 0x44fb70 STP	XZR, XZR, [X0, #128]

      (911) 0x44fb74 STP	XZR, XZR, [X0, #144]

      (911) 0x44fb78 STP	XZR, XZR, [X0, #160]

      (911) 0x44fb7c ADD	X0, X0, #192

      (911) 0x44fb80 STP	XZR, XZR, [X8, #8]

      (911) 0x44fb84 CMP	X1, X0

      (911) 0x44fb88 B.NE	44fb4c

    (907) 0x44fb8c B	44f6e8

    (907) 0x44fb90 LDR	X4, [X22, #24]

    (907) 0x44fb94 SUB	X3, X21, X30

    (907) 0x44fb98 UBFM	X2, X3, #61, #60

    (907) 0x44fb9c ADD	X0, X4, X30,LSL #3

    (907) 0x44fba0 CBZ	X2, 44f714

0x44fba4 MOVZ	W1, #0

0x44fba8 BL	403890

0x44fbac B	44f714

    (907) 0x44fbb0 CBNZ	X6, 4501fc

    (907) 0x44fbb4 MOVN	X8, #61440

    (907) 0x44fbb8 CMP	X20, X8

    (907) 0x44fbbc B.HI	45025c

    (907) 0x44fbc0 UBFM	X22, X20, #61, #60

    (907) 0x44fbc4 ORR	X0, XZR, X22

    (907) 0x44fbc8 BL	403b10

    (907) 0x44fbcc STP	X20, X20, [X26, #8]

    (907) 0x44fbd0 STR	X0, [X26, #24]

    (907) 0x44fbd4 CBZ	X22, 44f758

0x44fbd8 ORR	X2, XZR, X22

0x44fbdc MOVZ	W1, #0

0x44fbe0 BL	403890

0x44fbe4 B	44f758

0x44fbe8 CBNZ	X1, 450274

    (907) 0x44fbec MOVN	X4, #61440

    (907) 0x44fbf0 CMP	X21, X4

    (907) 0x44fbf4 B.HI	450250

    (907) 0x44fbf8 UBFM	X28, X21, #61, #60

    (907) 0x44fbfc ORR	X0, XZR, X28

    (907) 0x44fc00 BL	403b10

    (907) 0x44fc04 STP	X21, X21, [X27, #8]

    (907) 0x44fc08 STR	X0, [X27, #24]

    (907) 0x44fc0c CBZ	X28, 44f590

0x44fc10 ORR	X2, XZR, X28

0x44fc14 MOVZ	W1, #0

0x44fc18 BL	403890

0x44fc1c B	44f590

    (907) 0x44fc20 CBNZ	X6, 450284

    (907) 0x44fc24 MOVN	X9, #61440

    (907) 0x44fc28 CMP	X21, X9

    (907) 0x44fc2c B.HI	450250

    (907) 0x44fc30 UBFM	X28, X21, #61, #60

    (907) 0x44fc34 ORR	X0, XZR, X28

    (907) 0x44fc38 BL	403b10

    (907) 0x44fc3c STP	X21, X21, [X27, #8]

    (907) 0x44fc40 STR	X0, [X27, #24]

    (907) 0x44fc44 CBZ	X28, 44f5c0

0x44fc48 ORR	X2, XZR, X28

0x44fc4c MOVZ	W1, #0

0x44fc50 BL	403890

0x44fc54 B	44f5c0

    (907) 0x44fc58 CBNZ	X11, 450294

    (907) 0x44fc5c MOVN	X14, #61440

    (907) 0x44fc60 CMP	X22, X14

    (907) 0x44fc64 B.HI	45025c

    (907) 0x44fc68 UBFM	X28, X22, #61, #60

    (907) 0x44fc6c ORR	X0, XZR, X28

    (907) 0x44fc70 BL	403b10

    (907) 0x44fc74 STP	X22, X22, [X27, #8]

    (907) 0x44fc78 STR	X0, [X27, #24]

    (907) 0x44fc7c CBZ	X28, 44f5e4

0x44fc80 ORR	X2, XZR, X28

0x44fc84 MOVZ	W1, #0

0x44fc88 BL	403890

0x44fc8c B	44f5e4

    (907) 0x44fc90 CBNZ	X16, 450198

    (907) 0x44fc94 MOVN	X30, #61440

    (907) 0x44fc98 CMP	X20, X30

    (907) 0x44fc9c B.HI	45025c

    (907) 0x44fca0 UBFM	X28, X20, #61, #60

    (907) 0x44fca4 ORR	X0, XZR, X28

    (907) 0x44fca8 BL	403b10

    (907) 0x44fcac STP	X20, X20, [X27, #8]

    (907) 0x44fcb0 STR	X0, [X27, #24]

    (907) 0x44fcb4 CBZ	X28, 44f608

0x44fcb8 ORR	X2, XZR, X28

0x44fcbc MOVZ	W1, #0

0x44fcc0 BL	403890

0x44fcc4 B	44f608

    (907) 0x44fcc8 CBNZ	X1, 4501a8

    (907) 0x44fccc MOVN	X4, #61440

    (907) 0x44fcd0 CMP	X21, X4

    (907) 0x44fcd4 B.HI	450250

    (907) 0x44fcd8 UBFM	X28, X21, #61, #60

    (907) 0x44fcdc ORR	X0, XZR, X28

    (907) 0x44fce0 BL	403b10

    (907) 0x44fce4 STP	X21, X21, [X27, #8]

    (907) 0x44fce8 STR	X0, [X27, #24]

    (907) 0x44fcec CBZ	X28, 44f638

0x44fcf0 ORR	X2, XZR, X28

0x44fcf4 MOVZ	W1, #0

0x44fcf8 BL	403890

0x44fcfc B	44f638

    (907) 0x44fd00 CBNZ	X5, 4501b8

    (907) 0x44fd04 MOVN	X8, #61440

    (907) 0x44fd08 CMP	X21, X8

    (907) 0x44fd0c B.HI	450250

    (907) 0x44fd10 UBFM	X28, X21, #61, #60

    (907) 0x44fd14 ORR	X0, XZR, X28

    (907) 0x44fd18 BL	403b10

    (907) 0x44fd1c STP	X21, X21, [X27, #8]

    (907) 0x44fd20 STR	X0, [X27, #24]

    (907) 0x44fd24 CBZ	X28, 44f66c

0x44fd28 MOVZ	W1, #0

0x44fd2c ORR	X2, XZR, X28

0x44fd30 BL	403890

0x44fd34 LDR	X21, [X19, #856]

0x44fd38 ADD	X26, X19, #856

0x44fd3c LDR	X9, [X26, #8]

0x44fd40 SUB	X1, X9, X21

0x44fd44 SBFM	X10, X1, #2, #63

0x44fd48 CMP	X22, X10

0x44fd4c B.LS	44f688

    (907) 0x44fd50 LDR	X13, [X26, #16]

    (907) 0x44fd54 MOVN	X11, #57344

    (907) 0x44fd58 SUB	X27, X22, X10

    (907) 0x44fd5c SUB	X12, X11, X10

    (907) 0x44fd60 SUB	X14, X13, X9

    (907) 0x44fd64 CMP	X27, X14,ASR #2

    (907) 0x44fd68 B.LS	450164

    (907) 0x44fd6c CMP	X27, X12

    (907) 0x44fd70 B.HI	450334

    (907) 0x44fd74 CMP	X10, X27

    (907) 0x44fd78 CSEL	X15, X10, X27, #2

    (907) 0x44fd7c ADDS	X16, X15, X10

    (907) 0x44fd80 B.CS	450340

    (907) 0x44fd84 CBNZ	X16, 450300

0x44fd88 ORR	X3, XZR, X1

0x44fd8c MOVZ	X28, #0

0x44fd90 MOVZ	X18, #0

    (907) 0x44fd94 SUBS	X30, X27, #1

    (907) 0x44fd98 STR	WZR, [X18, X1]

    (907) 0x44fd9c ADD	X4, X18, X1

    (907) 0x44fda0 B.EQ	44fdbc

    (907) 0x44fda4 UBFM	X2, X30, #62, #61

    (907) 0x44fda8 ADD	X0, X4, #4

    (907) 0x44fdac STP	X3, X18, [SP, #96]

    (907) 0x44fdb0 MOVZ	W1, #0

    (907) 0x44fdb4 BL	403890

    (907) 0x44fdb8 LDP	X3, X18, [SP, #96]

    (907) 0x44fdbc CMP	X3, #0

    (907) 0x44fdc0 B.GT	4502a4

    (907) 0x44fdc4 CBNZ	X21, 4502f4

    (907) 0x44fdc8 ADD	X22, X18, X22,LSL #2

    (907) 0x44fdcc STR	X18, [X19, #856]

    (907) 0x44fdd0 STP	X22, X28, [X26, #8]

    (907) 0x44fdd4 B	44f68c

    (907) 0x44fdd8 CBNZ	X10, 4501c8

    (907) 0x44fddc MOVN	X12, #61440

    (907) 0x44fde0 CMP	X21, X12

    (907) 0x44fde4 B.HI	450250

    (907) 0x44fde8 UBFM	X22, X21, #61, #60

    (907) 0x44fdec ORR	X0, XZR, X22

    (907) 0x44fdf0 BL	403b10

    (907) 0x44fdf4 STP	X21, X21, [X26, #8]

    (907) 0x44fdf8 STR	X0, [X26, #24]

    (907) 0x44fdfc CBZ	X22, 44f6c0

0x44fe00 ORR	X2, XZR, X22

0x44fe04 MOVZ	W1, #0

0x44fe08 BL	403890

0x44fe0c B	44f6c0

    (907) 0x44fe10 CBNZ	X14, 4501d8

    (907) 0x44fe14 ORR	X10, XZR, #3840

    (907) 0x44fe18 MOVK	X10, #1365

    (907) 0x44fe1c CMP	X21, X10

    (907) 0x44fe20 B.HI	450260

    (907) 0x44fe24 ADD	X11, X21, X21,LSL #1

    (907) 0x44fe28 UBFM	X27, X11, #61, #60

    (907) 0x44fe2c ORR	X0, XZR, X27

    (907) 0x44fe30 BL	403b10

    (907) 0x44fe34 ADD	X12, X0, X27

    (907) 0x44fe38 STP	X21, X21, [X26, #8]

    (907) 0x44fe3c STR	X0, [X26, #24]

    (907) 0x44fe40 CMP	X12, X0

    (907) 0x44fe44 B.EQ	44f6ec

    (907) 0x44fe48 MOVZ	X26, #43691

    (907) 0x44fe4c SUB	X22, X12, X0

    (907) 0x44fe50 MOVK	X26, #43690

    (907) 0x44fe54 SUB	X13, X22, #24

    (907) 0x44fe58 MOVK	X26, #43690

    (907) 0x44fe5c UBFM	X14, X13, #3, #63

    (907) 0x44fe60 MOVK	X26, #2730

    (907) 0x44fe64 MADD	X15, X14, X26, XZR

    (907) 0x44fe68 ADD	X16, X15, #1

    (907) 0x44fe6c ANDS	X17, X16, #4224

    (907) 0x44fe70 B.EQ	44fef4

    (907) 0x44fe74 CMP	X17, #1

    (907) 0x44fe78 B.EQ	44fee0

    (907) 0x44fe7c CMP	X17, #2

    (907) 0x44fe80 B.EQ	44fed4

    (907) 0x44fe84 CMP	X17, #3

    (907) 0x44fe88 B.EQ	44fec8

    (907) 0x44fe8c CMP	X17, #4

    (907) 0x44fe90 B.EQ	44febc

    (907) 0x44fe94 CMP	X17, #5

    (907) 0x44fe98 B.EQ	44feb0

    (907) 0x44fe9c CMP	X17, #6

    (907) 0x44fea0 B.NE	4502e4

    (907) 0x44fea4 STP	XZR, XZR, [X0]

    (907) 0x44fea8 ADD	X0, X0, #24

    (907) 0x44feac STUR	XZR, [X0, #504]

    (907) 0x44feb0 STP	XZR, XZR, [X0]

    (907) 0x44feb4 ADD	X0, X0, #24

    (907) 0x44feb8 STUR	XZR, [X0, #504]

    (907) 0x44febc STP	XZR, XZR, [X0]

    (907) 0x44fec0 ADD	X0, X0, #24

    (907) 0x44fec4 STUR	XZR, [X0, #504]

    (907) 0x44fec8 STP	XZR, XZR, [X0]

    (907) 0x44fecc ADD	X0, X0, #24

    (907) 0x44fed0 STUR	XZR, [X0, #504]

    (907) 0x44fed4 STP	XZR, XZR, [X0]

    (907) 0x44fed8 ADD	X0, X0, #24

    (907) 0x44fedc STUR	XZR, [X0, #504]

    (907) 0x44fee0 STP	XZR, XZR, [X0]

    (907) 0x44fee4 ADD	X0, X0, #24

    (907) 0x44fee8 STUR	XZR, [X0, #504]

    (907) 0x44feec CMP	X12, X0

    (907) 0x44fef0 B.EQ	44f6ec

      (910) 0x44fef4 ADD	X18, X0, #168

      (910) 0x44fef8 STP	XZR, XZR, [X0]

      (910) 0x44fefc STP	XZR, XZR, [X0, #16]

      (910) 0x44ff00 STP	XZR, XZR, [X0, #32]

      (910) 0x44ff04 STP	XZR, XZR, [X0, #48]

      (910) 0x44ff08 STP	XZR, XZR, [X0, #64]

      (910) 0x44ff0c STP	XZR, XZR, [X0, #80]

      (910) 0x44ff10 STP	XZR, XZR, [X0, #96]

      (910) 0x44ff14 STP	XZR, XZR, [X0, #112]

      (910) 0x44ff18 STP	XZR, XZR, [X0, #128]

      (910) 0x44ff1c STP	XZR, XZR, [X0, #144]

      (910) 0x44ff20 STP	XZR, XZR, [X0, #160]

      (910) 0x44ff24 ADD	X0, X0, #192

      (910) 0x44ff28 STP	XZR, XZR, [X18, #8]

      (910) 0x44ff2c CMP	X12, X0

      (910) 0x44ff30 B.NE	44fef4

    (907) 0x44ff34 B	44f6ec

    (907) 0x44ff38 CBNZ	X1, 4501ec

    (907) 0x44ff3c MOVN	X2, #61440

    (907) 0x44ff40 CMP	X21, X2

    (907) 0x44ff44 B.HI	450250

    (907) 0x44ff48 UBFM	X27, X21, #61, #60

    (907) 0x44ff4c ORR	X0, XZR, X27

    (907) 0x44ff50 BL	403b10

    (907) 0x44ff54 STP	X21, X21, [X22, #8]

    (907) 0x44ff58 STR	X0, [X22, #24]

    (907) 0x44ff5c CBZ	X27, 44f718

0x44ff60 ORR	X2, XZR, X27

0x44ff64 MOVZ	W1, #0

0x44ff68 BL	403890

0x44ff6c B	44f718

    (907) 0x44ff70 CBNZ	X10, 45020c

    (907) 0x44ff74 MOVN	X13, #61440

    (907) 0x44ff78 CMP	X20, X13

    (907) 0x44ff7c B.HI	45025c

    (907) 0x44ff80 UBFM	X27, X20, #61, #60

    (907) 0x44ff84 ORR	X0, XZR, X27

    (907) 0x44ff88 BL	403b10

    (907) 0x44ff8c STP	X20, X20, [X26, #8]

    (907) 0x44ff90 STR	X0, [X26, #24]

    (907) 0x44ff94 CBZ	X27, 44f798

0x44ff98 ORR	X2, XZR, X27

0x44ff9c MOVZ	W1, #0

0x44ffa0 BL	403890

0x44ffa4 B	44f798

    (907) 0x44ffa8 CBNZ	X15, 45021c

    (907) 0x44ffac MOVN	X17, #61440

    (907) 0x44ffb0 CMP	X21, X17

    (907) 0x44ffb4 B.HI	450250

(909) 0x44ffb8 UBFM	X22, X21, #61, #60

(909) 0x44ffbc ORR	X0, XZR, X22

(909) 0x44ffc0 BL	403b10

(909) 0x44ffc4 STP	X21, X21, [X26, #8]

(909) 0x44ffc8 STR	X0, [X26, #24]

(909) 0x44ffcc CBZ	X22, 44f7e0

0x44ffd0 ORR	X2, XZR, X22

0x44ffd4 MOVZ	W1, #0

0x44ffd8 BL	403890

0x44ffdc B	44f7e0

(909) 0x44ffe0 CBNZ	X3, 45022c

(909) 0x44ffe4 ORR	X27, XZR, #3840

(909) 0x44ffe8 MOVK	X27, #1365

(909) 0x44ffec CMP	X20, X27

(909) 0x44fff0 B.HI	45025c

(909) 0x44fff4 MOVZ	W26, #24

(909) 0x44fff8 SMADDL	X28, W23, W26, XZR

(909) 0x44fffc ORR	X0, XZR, X28

(909) 0x450000 BL	403b10

(909) 0x450004 ADD	X14, X0, X28

(909) 0x450008 STP	X20, X20, [X21, #8]

(909) 0x45000c STR	X0, [X21, #24]

(909) 0x450010 CMP	X14, X0

(909) 0x450014 B.EQ	450110

(909) 0x450018 MOVZ	X15, #43691

(909) 0x45001c SUB	X20, X14, X0

(909) 0x450020 MOVK	X15, #43690

(909) 0x450024 SUB	X16, X20, #24

(909) 0x450028 MOVK	X15, #43690

(909) 0x45002c UBFM	X17, X16, #3, #63

(909) 0x450030 MOVK	X15, #2730

(909) 0x450034 MADD	X22, X17, X15, XZR

(909) 0x450038 ADD	X21, X22, #1

(909) 0x45003c ANDS	X18, X21, #4224

(909) 0x450040 B.EQ	4500d0

(909) 0x450044 CMP	X18, #1

(909) 0x450048 B.EQ	4500bc

(909) 0x45004c CMP	X18, #2

(909) 0x450050 B.EQ	4500b0

(909) 0x450054 CMP	X18, #3

(909) 0x450058 B.EQ	4500a4

(909) 0x45005c CMP	X18, #4

(909) 0x450060 B.EQ	450098

(909) 0x450064 CMP	X18, #5

(909) 0x450068 B.EQ	45008c

(909) 0x45006c CMP	X18, #6

(909) 0x450070 B.EQ	450080

(909) 0x450074 STP	XZR, XZR, [X0]

(909) 0x450078 ADD	X0, X0, #24

(909) 0x45007c STUR	XZR, [X0, #504]

(909) 0x450080 STP	XZR, XZR, [X0]

(909) 0x450084 ADD	X0, X0, #24

(909) 0x450088 STUR	XZR, [X0, #504]

(909) 0x45008c STP	XZR, XZR, [X0]

(909) 0x450090 ADD	X0, X0, #24

(909) 0x450094 STUR	XZR, [X0, #504]

(909) 0x450098 STP	XZR, XZR, [X0]

(909) 0x45009c ADD	X0, X0, #24

(909) 0x4500a0 STUR	XZR, [X0, #504]

(909) 0x4500a4 STP	XZR, XZR, [X0]

(909) 0x4500a8 ADD	X0, X0, #24

(909) 0x4500ac STUR	XZR, [X0, #504]

(909) 0x4500b0 STP	XZR, XZR, [X0]

(909) 0x4500b4 ADD	X0, X0, #24

(909) 0x4500b8 STUR	XZR, [X0, #504]

(909) 0x4500bc STP	XZR, XZR, [X0]

(909) 0x4500c0 ADD	X0, X0, #24

(909) 0x4500c4 STUR	XZR, [X0, #504]

(909) 0x4500c8 CMP	X14, X0

(909) 0x4500cc B.EQ	450110

  (912) 0x4500d0 ADD	X30, X0, #168

  (912) 0x4500d4 STP	XZR, XZR, [X0]

  (912) 0x4500d8 STP	XZR, XZR, [X0, #16]

  (912) 0x4500dc STP	XZR, XZR, [X0, #32]

  (912) 0x4500e0 STP	XZR, XZR, [X0, #48]

  (912) 0x4500e4 STP	XZR, XZR, [X0, #64]

  (912) 0x4500e8 STP	XZR, XZR, [X0, #80]

  (912) 0x4500ec STP	XZR, XZR, [X0, #96]

  (912) 0x4500f0 STP	XZR, XZR, [X0, #112]

  (912) 0x4500f4 STP	XZR, XZR, [X0, #128]

  (912) 0x4500f8 STP	XZR, XZR, [X0, #144]

  (912) 0x4500fc STP	XZR, XZR, [X0, #160]

  (912) 0x450100 ADD	X0, X0, #192

  (912) 0x450104 STP	XZR, XZR, [X30, #8]

  (912) 0x450108 CMP	X14, X0

  (912) 0x45010c B.NE	4500d0

(909) 0x450110 LDRSW	X25, [X19, #1152]

(909) 0x450114 B	44f930

(909) 0x450118 CBNZ	X1, 450240

(909) 0x45011c MOVN	X4, #61440

(909) 0x450120 CMP	X25, X4

(909) 0x450124 B.HI	45025c

(909) 0x450128 UBFM	X27, X25, #61, #60

(909) 0x45012c ORR	X0, XZR, X27

(909) 0x450130 BL	403b10

(909) 0x450134 STP	X25, X25, [X19, #8]

(909) 0x450138 STR	X0, [X19, #24]

(909) 0x45013c CBZ	X27, 44f970

0x450140 ORR	X2, XZR, X27

0x450144 MOVZ	W1, #0

0x450148 LDP	X19, X20, [SP, #16]

0x45014c LDP	X21, X22, [SP, #32]

0x450150 LDP	X23, X24, [SP, #48]

0x450154 LDP	X25, X26, [SP, #64]

0x450158 LDP	X27, X28, [SP, #80]

0x45015c LDP	X29, X30, [SP], #112

0x450160 B	403890

    (907) 0x450164 ORR	X21, XZR, X9

    (907) 0x450168 SUBS	X6, X27, #1

    (907) 0x45016c STR	WZR, [X21], #4

    (907) 0x450170 B.EQ	44fa58

    (907) 0x450174 ADD	X7, X21, X6,LSL #2

    (907) 0x450178 ORR	X0, XZR, X21

    (907) 0x45017c MOVZ	W1, #0

    (907) 0x450180 SUB	X8, X7, X9

    (907) 0x450184 SUB	X2, X8, #4

    (907) 0x450188 ADD	X21, X21, X2

    (907) 0x45018c BL	403890

    (907) 0x450190 STR	X21, [X26, #8]

    (907) 0x450194 B	44f68c

    (907) 0x450198 UBFM	X1, X16, #61, #60

    (907) 0x45019c LDR	X0, [X27, #24]

    (907) 0x4501a0 BL	4039f0

    (907) 0x4501a4 B	44fc94

    (907) 0x4501a8 UBFM	X1, X1, #61, #60

    (907) 0x4501ac LDR	X0, [X27, #24]

    (907) 0x4501b0 BL	4039f0

    (907) 0x4501b4 B	44fccc

    (907) 0x4501b8 UBFM	X1, X5, #61, #60

    (907) 0x4501bc LDR	X0, [X27, #24]

    (907) 0x4501c0 BL	4039f0

    (907) 0x4501c4 B	44fd04

    (907) 0x4501c8 UBFM	X1, X10, #61, #60

    (907) 0x4501cc LDR	X0, [X26, #24]

    (907) 0x4501d0 BL	4039f0

    (907) 0x4501d4 B	44fddc

    (907) 0x4501d8 ADD	X9, X14, X14,LSL #1

    (907) 0x4501dc LDR	X0, [X26, #24]

    (907) 0x4501e0 UBFM	X1, X9, #61, #60

    (907) 0x4501e4 BL	4039f0

    (907) 0x4501e8 B	44fe14

    (907) 0x4501ec UBFM	X1, X1, #61, #60

    (907) 0x4501f0 LDR	X0, [X22, #24]

    (907) 0x4501f4 BL	4039f0

    (907) 0x4501f8 B	44ff3c

    (907) 0x4501fc UBFM	X1, X6, #61, #60

    (907) 0x450200 LDR	X0, [X26, #24]

    (907) 0x450204 BL	4039f0

    (907) 0x450208 B	44fbb4

    (907) 0x45020c UBFM	X1, X10, #61, #60

    (907) 0x450210 LDR	X0, [X26, #24]

    (907) 0x450214 BL	4039f0

    (907) 0x450218 B	44ff74

    (907) 0x45021c UBFM	X1, X15, #61, #60

    (907) 0x450220 LDR	X0, [X26, #24]

    (907) 0x450224 BL	4039f0

    (907) 0x450228 B	44ffac

(909) 0x45022c ADD	X25, X3, X3,LSL #1

(909) 0x450230 LDR	X0, [X21, #24]

(909) 0x450234 UBFM	X1, X25, #61, #60

(909) 0x450238 BL	4039f0

(909) 0x45023c B	44ffe4

(909) 0x450240 UBFM	X1, X1, #61, #60

(909) 0x450244 LDR	X0, [X19, #24]

(909) 0x450248 BL	4039f0

(909) 0x45024c B	45011c

    (907) 0x450250 MOVN	X0, #57344

    (907) 0x450254 CMP	X21, X0

    (907) 0x450258 B.LS	450270

  (906) 0x45025c BL	403d60

    (908) 0x450260 ORR	X10, XZR, #3841

    (908) 0x450264 MOVK	X10, #2730

    (908) 0x450268 CMP	X21, X10

    (908) 0x45026c B.HI	45025c

    (907) 0x450270 BL	403e40

    (907) 0x450274 UBFM	X1, X1, #61, #60

    (907) 0x450278 LDR	X0, [X27, #24]

    (907) 0x45027c BL	4039f0

    (907) 0x450280 B	44fbec

    (907) 0x450284 UBFM	X1, X6, #61, #60

    (907) 0x450288 LDR	X0, [X27, #24]

    (907) 0x45028c BL	4039f0

    (907) 0x450290 B	44fc24

    (907) 0x450294 UBFM	X1, X11, #61, #60

    (907) 0x450298 LDR	X0, [X27, #24]

    (907) 0x45029c BL	4039f0

    (907) 0x4502a0 B	44fc5c

    (907) 0x4502a4 ORR	X1, XZR, X21

    (907) 0x4502a8 ORR	X0, XZR, X18

    (907) 0x4502ac ORR	X2, XZR, X3

    (907) 0x4502b0 BL	4036e0

    (907) 0x4502b4 LDR	X5, [X26, #16]

    (907) 0x4502b8 ORR	X18, XZR, X0

    (907) 0x4502bc SUB	X1, X5, X21

    (907) 0x4502c0 ORR	X0, XZR, X21

    (907) 0x4502c4 STR	X18, [SP, #96]

    (907) 0x4502c8 BL	4039f0

    (907) 0x4502cc LDR	X18, [SP, #96]

    (907) 0x4502d0 B	44fdc8

    (907) 0x4502d4 STP	XZR, XZR, [X0]

    (907) 0x4502d8 ADD	X0, X0, #24

    (907) 0x4502dc STUR	XZR, [X0, #504]

    (907) 0x4502e0 B	44fafc

    (907) 0x4502e4 STP	XZR, XZR, [X0]

    (907) 0x4502e8 ADD	X0, X0, #24

    (907) 0x4502ec STUR	XZR, [X0, #504]

    (907) 0x4502f0 B	44fea4

    (907) 0x4502f4 LDR	X2, [X26, #16]

    (907) 0x4502f8 SUB	X1, X2, X21

    (907) 0x4502fc B	4502c0

    (907) 0x450300 CMP	X16, X11

    (907) 0x450304 CSEL	X17, X16, X11, #9

    (907) 0x450308 UBFM	X28, X17, #62, #61

    (907) 0x45030c ORR	X0, XZR, X28

    (907) 0x450310 STR	X1, [SP, #96]

    (907) 0x450314 BL	403b10

    (907) 0x450318 ORR	X18, XZR, X0

    (907) 0x45031c ADD	X28, X0, X28

    (907) 0x450320 LDR	X0, [X26, #8]

    (907) 0x450324 LDR	X21, [X19, #856]

    (907) 0x450328 LDR	X1, [SP, #96]

    (907) 0x45032c SUB	X3, X0, X21

    (907) 0x450330 B	44fd94

    (907) 0x450334 ADRP	X19,

    (907) 0x450338 ADD	X0, X19, #3272

    (907) 0x45033c BL	403b50

    (907) 0x450340 ORR	X28, XZR, #7998

    (907) 0x450344 B	45030c

0x450348 MOVZ	X0, #16

0x45034c BL	403cb0

0x450350 ADRP	X13,

0x450354 ORR	X19, XZR, X0

0x450358 ADD	X1, X13, #3208

0x45035c BL	4038c0

(905) 0x450360 ADRP	X16,

(905) 0x450364 ADRP	X17,

(905) 0x450368 LDR	X2, [X16, #3840]

(905) 0x45036c ORR	X0, XZR, X19

(905) 0x450370 LDR	X1, [X17, #3920]

(905) 0x450374 BL	403d20

(905) 0x450378 MOVZ	X0, #16

(905) 0x45037c ADRP	X28,

(905) 0x450380 BL	403cb0

(905) 0x450384 ADD	X1, X28, #3208

(905) 0x450388 ORR	X19, XZR, X0

(905) 0x45038c BL	4038c0

(905) 0x450390 B	450360

(904) 0x450394 ORR	X15, XZR, X0

(904) 0x450398 ORR	X0, XZR, X19

(904) 0x45039c ORR	X22, XZR, X15

(904) 0x4503a0 BL	403c60

(904) 0x4503a4 ORR	X0, XZR, X22

(904) 0x4503a8 BL	403aa0

(904) 0x4503ac B	450394

0x4503b0 MOVZ	X0, #16

0x4503b4 ADRP	X26,

0x4503b8 BL	403cb0

0x4503bc ADD	X1, X26, #3208

0x4503c0 ORR	X19, XZR, X0

0x4503c4 BL	4038c0

0x4503c8 B	450360

0x4503cc MOVZ	X0, #16

0x4503d0 BL	403cb0

0x4503d4 ADRP	X14,

0x4503d8 ORR	X19, XZR, X0

0x4503dc ADD	X1, X14, #3208

0x4503e0 BL	4038c0

0x4503e4 B	450360

0x4503e8 B	450394

0x4503ec B	450394

0x4503f0 MOVZ	X0, #16

0x4503f4 ADRP	X20,

0x4503f8 BL	403cb0

0x4503fc ADD	X1, X20, #3208

0x450400 ORR	X19, XZR, X0

0x450404 BL	4038c0

0x450408 B	450360

0x45040c MOVZ	X0, #16

0x450410 BL	403cb0

0x450414 ADRP	X5,

0x450418 ORR	X19, XZR, X0

0x45041c ADD	X1, X5, #3208

0x450420 BL	4038c0

0x450424 B	450360

0x450428 B	450394

0x45042c B	450394

0x450430 MOVZ	X0, #16

0x450434 BL	403cb0

0x450438 ADRP	X7,

0x45043c ORR	X19, XZR, X0

0x450440 ADD	X1, X7, #3208

0x450444 BL	4038c0

0x450448 B	450360

0x45044c MOVZ	X0, #16

0x450450 BL	403cb0

0x450454 ADRP	X6,

0x450458 ORR	X19, XZR, X0

0x45045c ADD	X1, X6, #3208

0x450460 BL	4038c0

0x450464 B	450360

0x450468 B	450394

0x45046c B	450394

0x450470 MOVZ	X0, #16

0x450474 BL	403cb0

0x450478 ADRP	X11,

0x45047c ORR	X19, XZR, X0

0x450480 ADD	X1, X11, #3208

0x450484 BL	4038c0

0x450488 B	450360

0x45048c MOVZ	X0, #16

0x450490 BL	403cb0

0x450494 ADRP	X12,

0x450498 ORR	X19, XZR, X0

0x45049c ADD	X1, X12, #3208

0x4504a0 BL	4038c0

0x4504a4 B	450360

0x4504a8 B	450394

0x4504ac B	450394

0x4504b0 MOVZ	X0, #16

0x4504b4 BL	403cb0

0x4504b8 ADRP	X9,

0x4504bc ORR	X19, XZR, X0

0x4504c0 ADD	X1, X9, #3208

0x4504c4 BL	4038c0

0x4504c8 B	450360

0x4504cc MOVZ	X0, #16

0x4504d0 ADRP	X25,

0x4504d4 BL	403cb0

0x4504d8 ADD	X1, X25, #3208

0x4504dc ORR	X19, XZR, X0

0x4504e0 BL	4038c0

0x4504e4 B	450360

0x4504e8 B	450394

0x4504ec B	450394

0x4504f0 MOVZ	X0, #16

0x4504f4 BL	403cb0

0x4504f8 ADRP	X8,

0x4504fc ORR	X19, XZR, X0

0x450500 ADD	X1, X8, #3208

0x450504 BL	4038c0

0x450508 B	450360

0x45050c MOVZ	X0, #16

0x450510 BL	403cb0

0x450514 ADRP	X2,

0x450518 ORR	X19, XZR, X0

0x45051c ADD	X1, X2, #3208

0x450520 BL	4038c0

0x450524 B	450360

0x450528 B	450394

0x45052c B	450394

0x450530 HINT	#0

0x450534 HINT	#0

0x450538 HINT	#0

0x45053c HINT	#0

Coverage (%)	Name	Source Location	Module
►60.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:83	exec
○	main._omp_fn.0	miniqmc.cpp:389	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►40.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:84	exec
○	main._omp_fn.0	miniqmc.cpp:389	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:61-79
Module	exec

The function is defined in:

/usr/include/c++/11/bits/stl_uninitialized.h:1009-1011
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:61-67,73-79
/usr/include/c++/11/bits/stl_construct.h:108
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:101-103
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/usr/include/c++/11/bits/stl_algobase.h:911,923-924,1115-1120
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:185-188,195-197,296-302
/usr/include/c++/11/bits/alloc_traits.h:492
/usr/include/c++/11/bits/stl_vector.h:346,353,919,939-942,1758-1759,1794-1798
/usr/include/c++/11/ext/new_allocator.h:105-111,121,139
/usr/include/c++/11/bits/vector.tcc:618-623,640,648,677-680
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 48.50 to 6.06 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.50 to 24.50 cycles (1.98x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	228
loop length	912
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	48.50	48.50	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50
cycles	48.50	48.50	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.00
Overall L1	48.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.50 cycles. At this rate:

2% of peak load performance is reached (2.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44f520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0, #1160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X0, #608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSEL W23, W2, W1, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X20, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X0, X1, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SMADDL X21, W26, W23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X22, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [X19, #584]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X20, [X19, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [X19, #600]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 4503f0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xed0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 44fbe8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 44f98c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f58c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5e0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f604 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f634 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f668 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f6bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f714 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f758 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X1, 450274 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xd54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f590 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5e4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f608 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f638 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X19, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X19, #856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X10, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 44f688 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f6c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f718 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f798 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f7e0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 403890 <@plt_start@+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X13, <49e350>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X13, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X26, <49e3b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X26, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X14, <49e3d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X20, <49e3f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X20, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X5, <49e414>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X7, <49e438>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X7, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X6, <49e454>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X6, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X11, <49e478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <49e494>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X9, <49e4b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X25, <49e4d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X25, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <49e4f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X2, <49e514>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X2, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	DiracDeterminantRef.cpp:61-79
Module	exec

The function is defined in:

/usr/include/c++/11/bits/stl_uninitialized.h:1009-1011
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:61-67,73-79
/usr/include/c++/11/bits/stl_construct.h:108
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:101-103
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/usr/include/c++/11/bits/stl_algobase.h:911,923-924,1115-1120
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:185-188,195-197,296-302
/usr/include/c++/11/bits/alloc_traits.h:492
/usr/include/c++/11/bits/stl_vector.h:346,353,919,939-942,1758-1759,1794-1798
/usr/include/c++/11/ext/new_allocator.h:105-111,121,139
/usr/include/c++/11/bits/vector.tcc:618-623,640,648,677-680
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:62

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.50 to 24.50 cycles (1.98x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	228
loop length	912
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	48.50	48.50	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50
cycles	48.50	48.50	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.00
Overall L1	48.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.50 cycles. At this rate:

2% of peak load performance is reached (2.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44f520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0, #1160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X0, #608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSEL W23, W2, W1, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X20, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X0, X1, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SMADDL X21, W26, W23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SBFM X22, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [X19, #584]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X20, [X19, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [X19, #600]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 4503f0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xed0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 44fbe8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 44f98c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f58c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5e0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f604 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f634 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f668 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f6bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f714 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f758 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X1, 450274 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xd54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f590 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f5e4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f608 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f638 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X19, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X19, #856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X10, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 44f688 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f6c0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f718 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f798 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403890 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44f7e0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 403890 <@plt_start@+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X13, <49e350>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X13, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X26, <49e3b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X26, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X14, <49e3d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X20, <49e3f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X20, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X5, <49e414>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X7, <49e438>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X7, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X6, <49e454>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X6, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X11, <49e478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <49e494>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X9, <49e4b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X25, <49e4d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X25, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <49e4f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cb0 <@plt_start@+0x630>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X2, <49e514>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X2, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4038c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450360 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::resize(int, int)–	0.04	0.02
○Loop 904 - OhmmsVector.h:186-186 - exec	0	0
▼Loop 909 - stl_algobase.h:911-1120 - exec–	0	0
○Loop 913 - stl_algobase.h:911-911 - exec	0	0
○Loop 912 - stl_algobase.h:911-911 - exec	0	0
▼Loop 906 - new_allocator.h:105-139 - exec–	0	0
○Loop 908 - new_allocator.h:109-109 - exec	0	0
▼Loop 907 - stl_algobase.h:911-1120 - exec–	0	0
○Loop 910 - stl_algobase.h:911-911 - exec	0.04	0.02
○Loop 911 - stl_algobase.h:911-911 - exec	0	0
○Loop 905 - OhmmsVector.h:186-186 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code