OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const*, double*, double*, double*, double*, int*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const, double, do ...	Module: exec	Source: BsplineFunctor.h:266-339 [...]	Coverage: 0.03%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 266 - 339

--------------------------------------------------------------------------------

266: inline void BsplineFunctor<T>::evaluateVGL(const int iat,

[...]

276:   real_type dSquareDeltaRinv = DeltaRInv * DeltaRInv;

[...]

283:   int iCount                 = 0;

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

[...]

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

337:     // clang-format on

338:   }

339: }

/usr/include/c++/11/bits/stl_vector.h: 1061 - 1061

--------------------------------------------------------------------------------

1061:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

0x437600 CNTB	X12, ALL

0x437604 MOVZ	X13, #25

0x437608 ADD	X11, SP, #0

0x43760c MADD	X8, X12, X13, XZR

0x437610 ADD	X9, X8, #64

(664) 0x437614 CMP	X9, #15

(664) 0x437618 B.LT	43762c

(664) 0x43761c SUB	SP, SP, #15

(664) 0x437620 STR	XZR, [SP]

(664) 0x437624 SUB	X9, X9, #15

(664) 0x437628 B	437614

0x43762c SUB	SP, SP, X9,UXTX

0x437630 LDR	D21, [X0, #568]

0x437634 ADDVL	X10, SP, #25

0x437638 SUB	W3, W3, W2

0x43763c LDP	X15, X16, [X10, #64]

0x437640 FMUL	D23, D21, D21

0x437644 CMP	W3, #0

0x437648 B.LE	437ef0

0x43764c SBFM	X17, X2, #61, #31

0x437650 ANDS	W14, W3, #128

0x437654 LDR	D0, [X0, #8]

0x437658 ADD	X18, X4, X17

0x43765c MOVZ	W8, #0

0x437660 MOVZ	X4, #0

0x437664 B.EQ	437788

0x437668 CMP	W14, #1

0x43766c B.EQ	437758

0x437670 CMP	W14, #2

0x437674 B.EQ	437730

0x437678 CMP	W14, #3

0x43767c B.EQ	437720

0x437680 CMP	W14, #4

0x437684 B.EQ	4376f8

0x437688 CMP	W14, #5

0x43768c B.EQ	4376e8

0x437690 CMP	W14, #6

0x437694 B.EQ	4376c0

0x437698 LDR	D1, [X18]

0x43769c FCMPE	D0, D1

0x4376a0 B.LS	4376bc

0x4376a4 CMP	W2, W1

0x4376a8 B.EQ	4376bc

0x4376ac MOVZ	X4, #0

0x4376b0 MOVZ	W8, #1

0x4376b4 STR	WZR, [X16, X4]

0x4376b8 STR	D1, [X15, X4]

0x4376bc MOVZ	X4, #1

0x4376c0 LDR	D2, [X18, X4,LSL #3]

0x4376c4 FCMPE	D0, D2

0x4376c8 B.LS	4376e4

0x4376cc ADD	W12, W2, W4

0x4376d0 CMP	W12, W1

0x4376d4 B.EQ	4376e4

0x4376d8 STR	W4, [X16, X8,SXTW #2]

0x4376dc STR	D2, [X15, X8,SXTW #3]

0x4376e0 ADD	W8, W8, #1

0x4376e4 ADD	X4, X4, #1

0x4376e8 LDR	D3, [X18, X4,LSL #3]

0x4376ec FCMPE	D0, D3

0x4376f0 B.GT	437f18

0x4376f4 ADD	X4, X4, #1

0x4376f8 LDR	D4, [X18, X4,LSL #3]

0x4376fc FCMPE	D0, D4

0x437700 B.LS	43771c

0x437704 ADD	W9, W2, W4

0x437708 CMP	W9, W1

0x43770c B.EQ	43771c

0x437710 STR	W4, [X16, X8,SXTW #2]

0x437714 STR	D4, [X15, X8,SXTW #3]

0x437718 ADD	W8, W8, #1

0x43771c ADD	X4, X4, #1

0x437720 LDR	D5, [X18, X4,LSL #3]

0x437724 FCMPE	D0, D5

0x437728 B.GT	437efc

(662) 0x43772c ADD	X4, X4, #1

(662) 0x437730 LDR	D6, [X18, X4,LSL #3]

(662) 0x437734 FCMPE	D0, D6

(662) 0x437738 B.LS	437754

(662) 0x43773c ADD	W10, W2, W4

(662) 0x437740 CMP	W10, W1

(662) 0x437744 B.EQ	437754

(662) 0x437748 STR	W4, [X16, X8,SXTW #2]

(662) 0x43774c STR	D6, [X15, X8,SXTW #3]

(662) 0x437750 ADD	W8, W8, #1

(662) 0x437754 ADD	X4, X4, #1

(662) 0x437758 LDR	D7, [X18, X4,LSL #3]

(662) 0x43775c FCMPE	D0, D7

(662) 0x437760 B.LS	43777c

(662) 0x437764 ADD	W14, W2, W4

(662) 0x437768 CMP	W14, W1

(662) 0x43776c B.EQ	43777c

(662) 0x437770 STR	W4, [X16, X8,SXTW #2]

(662) 0x437774 STR	D7, [X15, X8,SXTW #3]

(662) 0x437778 ADD	W8, W8, #1

(662) 0x43777c ADD	X4, X4, #1

(662) 0x437780 CMP	W3, W4

(662) 0x437784 B.LE	4378f0

  (663) 0x437788 LDR	D16, [X18, X4,LSL #3]

  (663) 0x43778c FCMPE	D0, D16

  (663) 0x437790 B.LS	4377b0

  (663) 0x437794 ADD	W12, W2, W4

  (663) 0x437798 CMP	W12, W1

  (663) 0x43779c B.EQ	4377b0

  (663) 0x4377a0 SBFM	X13, X8, #0, #31

  (663) 0x4377a4 ADD	W8, W8, #1

  (663) 0x4377a8 STR	W4, [X16, X13,LSL #2]

  (663) 0x4377ac STR	D16, [X15, X13,LSL #3]

  (663) 0x4377b0 ADD	X4, X4, #1

  (663) 0x4377b4 LDR	D17, [X18, X4,LSL #3]

  (663) 0x4377b8 FCMPE	D0, D17

  (663) 0x4377bc B.LS	4377dc

  (663) 0x4377c0 ADD	W9, W2, W4

  (663) 0x4377c4 CMP	W9, W1

  (663) 0x4377c8 B.EQ	4377dc

  (663) 0x4377cc SBFM	X11, X8, #0, #31

  (663) 0x4377d0 ADD	W8, W8, #1

  (663) 0x4377d4 STR	W4, [X16, X11,LSL #2]

  (663) 0x4377d8 STR	D17, [X15, X11,LSL #3]

  (663) 0x4377dc ADD	X10, X4, #1

  (663) 0x4377e0 LDR	D18, [X18, X10,LSL #3]

  (663) 0x4377e4 FCMPE	D0, D18

  (663) 0x4377e8 B.LS	437808

  (663) 0x4377ec ADD	W14, W2, W10

  (663) 0x4377f0 CMP	W14, W1

  (663) 0x4377f4 B.EQ	437808

  (663) 0x4377f8 SBFM	X12, X8, #0, #31

  (663) 0x4377fc ADD	W8, W8, #1

  (663) 0x437800 STR	W10, [X16, X12,LSL #2]

  (663) 0x437804 STR	D18, [X15, X12,LSL #3]

  (663) 0x437808 ADD	X13, X4, #2

  (663) 0x43780c LDR	D19, [X18, X13,LSL #3]

  (663) 0x437810 FCMPE	D0, D19

  (663) 0x437814 B.LS	437834

  (663) 0x437818 ADD	W9, W2, W13

  (663) 0x43781c CMP	W9, W1

  (663) 0x437820 B.EQ	437834

  (663) 0x437824 SBFM	X11, X8, #0, #31

  (663) 0x437828 ADD	W8, W8, #1

  (663) 0x43782c STR	W13, [X16, X11,LSL #2]

  (663) 0x437830 STR	D19, [X15, X11,LSL #3]

  (663) 0x437834 ADD	X10, X4, #3

  (663) 0x437838 LDR	D20, [X18, X10,LSL #3]

  (663) 0x43783c FCMPE	D0, D20

  (663) 0x437840 B.LS	437860

  (663) 0x437844 ADD	W14, W2, W10

  (663) 0x437848 CMP	W14, W1

  (663) 0x43784c B.EQ	437860

  (663) 0x437850 SBFM	X12, X8, #0, #31

  (663) 0x437854 ADD	W8, W8, #1

  (663) 0x437858 STR	W10, [X16, X12,LSL #2]

  (663) 0x43785c STR	D20, [X15, X12,LSL #3]

  (663) 0x437860 ADD	X13, X4, #4

  (663) 0x437864 LDR	D22, [X18, X13,LSL #3]

  (663) 0x437868 FCMPE	D0, D22

  (663) 0x43786c B.LS	43788c

  (663) 0x437870 ADD	W9, W2, W13

  (663) 0x437874 CMP	W9, W1

  (663) 0x437878 B.EQ	43788c

  (663) 0x43787c SBFM	X11, X8, #0, #31

  (663) 0x437880 ADD	W8, W8, #1

  (663) 0x437884 STR	W13, [X16, X11,LSL #2]

  (663) 0x437888 STR	D22, [X15, X11,LSL #3]

  (663) 0x43788c ADD	X10, X4, #5

  (663) 0x437890 LDR	D24, [X18, X10,LSL #3]

  (663) 0x437894 FCMPE	D0, D24

  (663) 0x437898 B.LS	4378b8

  (663) 0x43789c ADD	W14, W2, W10

  (663) 0x4378a0 CMP	W14, W1

  (663) 0x4378a4 B.EQ	4378b8

  (663) 0x4378a8 SBFM	X12, X8, #0, #31

  (663) 0x4378ac ADD	W8, W8, #1

  (663) 0x4378b0 STR	W10, [X16, X12,LSL #2]

  (663) 0x4378b4 STR	D24, [X15, X12,LSL #3]

  (663) 0x4378b8 ADD	X13, X4, #6

  (663) 0x4378bc LDR	D25, [X18, X13,LSL #3]

  (663) 0x4378c0 FCMPE	D0, D25

  (663) 0x4378c4 B.LS	4378e4

  (663) 0x4378c8 ADD	W9, W2, W13

  (663) 0x4378cc CMP	W9, W1

  (663) 0x4378d0 B.EQ	4378e4

  (663) 0x4378d4 SBFM	X11, X8, #0, #31

  (663) 0x4378d8 ADD	W8, W8, #1

  (663) 0x4378dc STR	W13, [X16, X11,LSL #2]

  (663) 0x4378e0 STR	D25, [X15, X11,LSL #3]

  (663) 0x4378e4 ADD	X4, X4, #7

  (663) 0x4378e8 CMP	W3, W4

  (663) 0x4378ec B.GT	437788

(662) 0x4378f0 CBZ	W8, 437ef0

0x4378f4 ADDVL	X1, SP, #19

0x4378f8 ADDVL	X18, SP, #18

0x4378fc STP	D8, D9, [SP]

0x437900 ADDVL	X10, SP, #17

0x437904 ADDVL	X14, SP, #16

0x437908 STP	D10, D11, [SP, #16]

0x43790c ADDVL	X13, SP, #14

0x437910 ADDVL	X11, SP, #12

0x437914 STP	D12, D13, [SP, #32]

0x437918 ADD	X1, X1, #64

0x43791c ADD	X18, X18, #64

0x437920 STP	D14, D15, [SP, #48]

0x437924 ADD	X10, X10, #64

0x437928 ADD	X14, X14, #64

0x43792c PTRUE	P0.B, ALL

0x437930 ADD	X13, X13, #64

0x437934 ADD	X11, X11, #64

0x437938 LD1RD	{Z12.D}, P0/Z, [X0, #20]

0x43793c ADDVL	X12, SP, #15

0x437940 ADDVL	X9, SP, #13

0x437944 LD1RD	{Z13.D}, P0/Z, [X0, #21]

0x437948 ADDVL	X4, SP, #11

0x43794c LD1RD	{Z27.D}, P0/Z, [X0, #26]

0x437950 LD1RD	{Z14.D}, P0/Z, [X0, #22]

0x437954 LD1RD	{Z15.D}, P0/Z, [X0, #24]

0x437958 LD1RD	{Z1.D}, P0/Z, [X0, #29]

0x43795c ADD	X12, X12, #64

0x437960 ADD	X9, X9, #64

0x437964 ADD	X4, X4, #64

0x437968 STR	Z12, [X1, MUL VL]

0x43796c ADDVL	X1, SP, #10

0x437970 STR	Z13, [X18, MUL VL]

0x437974 ADDVL	X18, SP, #9

0x437978 STR	Z27, [X13, MUL VL]

0x43797c ADD	X13, SP, #64

0x437980 STR	Z14, [X10, MUL VL]

0x437984 ADDVL	X10, SP, #8

0x437988 STR	Z15, [X14, MUL VL]

0x43798c ADD	X14, SP, #64

0x437990 STR	Z1, [X11, MUL VL]

0x437994 ADDVL	X11, SP, #20

0x437998 LD1RD	{Z26.D}, P0/Z, [X0, #25]

0x43799c LD1RD	{Z8.D}, P0/Z, [X0, #42]

0x4379a0 LD1RD	{Z0.D}, P0/Z, [X0, #28]

0x4379a4 ADD	X1, X1, #64

0x4379a8 LD1RD	{Z11.D}, P0/Z, [X0, #37]

0x4379ac LD1RD	{Z10.D}, P0/Z, [X0, #38]

0x4379b0 LD1RD	{Z9.D}, P0/Z, [X0, #41]

0x4379b4 LD1RD	{Z31.D}, P0/Z, [X0, #45]

0x4379b8 LD1RD	{Z30.D}, P0/Z, [X0, #46]

0x4379bc LD1RD	{Z29.D}, P0/Z, [X0, #49]

0x4379c0 LD1RD	{Z28.D}, P0/Z, [X0, #50]

0x4379c4 ADD	X7, X7, X17

0x4379c8 ADD	X6, X6, X17

0x4379cc ADD	X5, X5, X17

0x4379d0 ADD	X18, X18, #64

0x4379d4 STR	Z26, [X12, MUL VL]

0x4379d8 ADD	X10, X10, #64

0x4379dc ADDVL	X12, X14, #22

0x4379e0 STR	Z0, [X9, MUL VL]

0x4379e4 ADD	X11, X11, #64

0x4379e8 LD1RD	{Z2.D}, P0/Z, [X0, #30]

0x4379ec ADDVL	X9, X13, #23

0x4379f0 LD1RD	{Z24.D}, P0/Z, [X0, #11]

0x4379f4 LD1RD	{Z25.D}, P0/Z, [X0, #12]

0x4379f8 LD1RD	{Z3.D}, P0/Z, [X0, #32]

0x4379fc LD1RD	{Z4.D}, P0/Z, [X0, #33]

0x437a00 LD1RD	{Z5.D}, P0/Z, [X0, #34]

0x437a04 LD1RD	{Z6.D}, P0/Z, [X0, #3]

0x437a08 LD1RD	{Z7.D}, P0/Z, [X0, #4]

0x437a0c LD1RD	{Z16.D}, P0/Z, [X0, #5]

0x437a10 LD1RD	{Z17.D}, P0/Z, [X0, #6]

0x437a14 LD1RD	{Z18.D}, P0/Z, [X0, #7]

0x437a18 LD1RD	{Z19.D}, P0/Z, [X0, #8]

0x437a1c LD1RD	{Z20.D}, P0/Z, [X0, #9]

0x437a20 LD1RD	{Z22.D}, P0/Z, [X0, #10]

0x437a24 LD1RD	{Z12.D}, P0/Z, [X0, #13]

0x437a28 STR	Z24, [X13, #1, MUL VL]

0x437a2c STR	Z6, [X14, #7, MUL VL]

0x437a30 STR	Z7, [X14, #6, MUL VL]

0x437a34 STR	Z16, [X14, #5, MUL VL]

0x437a38 STR	Z17, [X14, #4, MUL VL]

0x437a3c STR	Z18, [X14, #3, MUL VL]

0x437a40 STR	Z20, [X13, #2, MUL VL]

0x437a44 MOVZ	X2, #0

0x437a48 ADDVL	X17, X15, #1

0x437a4c STR	Z2, [X4, MUL VL]

0x437a50 CNTW	X3, ALL

0x437a54 ADDVL	X4, SP, #21

0x437a58 STR	Z3, [X1, MUL VL]

0x437a5c STR	Z25, [X9, MUL VL]

0x437a60 STR	Z4, [X18, MUL VL]

0x437a64 STR	Z5, [X10, MUL VL]

0x437a68 STR	Z19, [X12, MUL VL]

0x437a6c STR	Z22, [X13, MUL VL]

0x437a70 STR	Z12, [X11, MUL VL]

0x437a74 LD1RD	{Z13.D}, P0/Z, [X0, #14]

0x437a78 ADD	X4, X4, #64

0x437a7c LDR	X1, [X0, #536]

0x437a80 STR	Z13, [X4, MUL VL]

0x437a84 LD1RD	{Z27.D}, P0/Z, [X0, #15]

0x437a88 LD1RD	{Z26.D}, P0/Z, [X0, #16]

0x437a8c LD1RD	{Z25.D}, P0/Z, [X0, #17]

0x437a90 LD1RD	{Z24.D}, P0/Z, [X0, #18]

0x437a94 ADDVL	X0, SP, #24

0x437a98 ADD	X0, X0, #64

0x437a9c DUP	Z21.D, Z21.D[0]

0x437aa0 DUP	Z23.D, Z23.D[0]

0x437aa4 WHILELO	P3.S, WZR, W8

0x437aa8 STR	Z8, [X0, MUL VL]

(661) 0x437aac PUNPKLO	P2.H, P3.B

(661) 0x437ab0 PUNPKHI	P1.H, P3.B

(661) 0x437ab4 LD1D	{Z13.D}, P2/Z, [X15, X2,LSL #3]

(661) 0x437ab8 LD1D	{Z6.D}, P1/Z, [X17, X2,LSL #3]

(661) 0x437abc FMUL	Z8.D, Z21.D, Z13.D

(661) 0x437ac0 FMUL	Z0.D, Z21.D, Z6.D

(661) 0x437ac4 MOVPRFX	Z14, Z8

(661) 0x437ac8 FCVTZS	Z14.S, P0/M, Z8.D

(661) 0x437acc MOVPRFX	Z15, Z0

(661) 0x437ad0 FCVTZS	Z15.S, P0/M, Z0.D

(661) 0x437ad4 ADDVL	X18, SP, #24

(661) 0x437ad8 UZP1	Z2.S, Z14.S, Z15.S

(661) 0x437adc MOVPRFX	Z4, Z2

(661) 0x437ae0 ADD	Z4.S, Z4.S, #1

(661) 0x437ae4 SUNPKLO	Z3.D, Z4

(661) 0x437ae8 MOVPRFX	Z12, Z2

(661) 0x437aec ADD	Z12.S, Z12.S, #3

(661) 0x437af0 LD1D	{Z19.D}, P2/Z, [X1, Z3.D,LSL #3]

(661) 0x437af4 SUNPKLO	Z14.D, Z12

(661) 0x437af8 SUNPKHI	Z3.D, Z12

(661) 0x437afc LD1D	{Z15.D}, P2/Z, [X1, Z14.D,LSL #3]

(661) 0x437b00 ADD	X18, X18, #64

(661) 0x437b04 ZIP2	Z1.S, Z2.S, Z2.S

(661) 0x437b08 SCVTF	Z1.D, P0/M, Z1.S

(661) 0x437b0c FSUB	Z1.D, Z8.D, Z1.D

(661) 0x437b10 MOVPRFX	Z22, Z28

(661) 0x437b14 FMLA	Z22.D, P0/M, Z29.D, Z1.D

(661) 0x437b18 FMUL	Z22.D, Z22.D, Z15.D

(661) 0x437b1c LDR	Z8, [X18, MUL VL]

(661) 0x437b20 ORR	Z5.D, Z8.D, Z8.D

(661) 0x437b24 FMLA	Z5.D, P0/M, Z9.D, Z1.D

(661) 0x437b28 FMUL	Z20.D, Z5.D, Z19.D

(661) 0x437b2c SUNPKHI	Z7.D, Z4

(661) 0x437b30 LD1D	{Z5.D}, P1/Z, [X1, Z3.D,LSL #3]

(661) 0x437b34 MOVPRFX	Z4, Z10

(661) 0x437b38 FMLA	Z4.D, P0/M, Z11.D, Z1.D

(661) 0x437b3c MOVPRFX	Z3, Z2

(661) 0x437b40 ADD	Z3.S, Z3.S, #2

(661) 0x437b44 SUNPKLO	Z16.D, Z2

(661) 0x437b48 SUNPKLO	Z12.D, Z3

(661) 0x437b4c LD1D	{Z16.D}, P2/Z, [X1, Z16.D,LSL #3]

(661) 0x437b50 LD1D	{Z12.D}, P2/Z, [X1, Z12.D,LSL #3]

(661) 0x437b54 FMAD	Z4.D, P0/M, Z16.D, Z20.D

(661) 0x437b58 MOVPRFX	Z20, Z30

(661) 0x437b5c FMLA	Z20.D, P0/M, Z31.D, Z1.D

(661) 0x437b60 FMAD	Z20.D, P0/M, Z12.D, Z22.D

(661) 0x437b64 FADD	Z4.D, Z4.D, Z20.D

(661) 0x437b68 FMUL	Z22.D, Z4.D, Z23.D

(661) 0x437b6c LD1W	{Z18.S}, P3/Z, [X16, X2,LSL #2]

(661) 0x437b70 LD1D	{Z7.D}, P1/Z, [X1, Z7.D,LSL #3]

(661) 0x437b74 SUNPKLO	Z17.D, Z18

(661) 0x437b78 SUNPKHI	Z14.D, Z2

(661) 0x437b7c SUNPKHI	Z3.D, Z3

(661) 0x437b80 LD1D	{Z14.D}, P1/Z, [X1, Z14.D,LSL #3]

(661) 0x437b84 LD1D	{Z3.D}, P1/Z, [X1, Z3.D,LSL #3]

(661) 0x437b88 ZIP1	Z2.S, Z2.S, Z2.S

(661) 0x437b8c ST1D	{Z22.D}, P2, [X7, Z17.D,LSL #3]

(661) 0x437b90 SCVTF	Z2.D, P0/M, Z2.S

(661) 0x437b94 FSUB	Z0.D, Z0.D, Z2.D

(661) 0x437b98 MOVPRFX	Z22, Z30

(661) 0x437b9c FMLA	Z22.D, P0/M, Z31.D, Z0.D

(661) 0x437ba0 MOVPRFX	Z20, Z28

(661) 0x437ba4 FMLA	Z20.D, P0/M, Z29.D, Z0.D

(661) 0x437ba8 FMLA	Z8.D, P0/M, Z9.D, Z0.D

(661) 0x437bac FMUL	Z2.D, Z20.D, Z5.D

(661) 0x437bb0 MOVPRFX	Z4, Z10

(661) 0x437bb4 FMLA	Z4.D, P0/M, Z11.D, Z0.D

(661) 0x437bb8 FMLA	Z2.D, P0/M, Z22.D, Z3.D

(661) 0x437bbc ADDVL	X14, SP, #12

(661) 0x437bc0 FMUL	Z22.D, Z8.D, Z7.D

(661) 0x437bc4 FMAD	Z4.D, P0/M, Z14.D, Z22.D

(661) 0x437bc8 SUNPKHI	Z18.D, Z18

(661) 0x437bcc FADD	Z20.D, Z2.D, Z4.D

(661) 0x437bd0 ADD	X14, X14, #64

(661) 0x437bd4 FMUL	Z4.D, Z20.D, Z23.D

(661) 0x437bd8 FDUP	Z2.D, #112

(661) 0x437bdc ST1D	{Z4.D}, P1, [X7, Z18.D,LSL #3]

(661) 0x437be0 ADDVL	X10, SP, #11

(661) 0x437be4 ADDVL	X13, SP, #9

(661) 0x437be8 LDR	Z8, [X14, MUL VL]

(661) 0x437bec ADDVL	X9, SP, #13

(661) 0x437bf0 ADD	X10, X10, #64

(661) 0x437bf4 FDIVR	Z13.D, P0/M, Z13.D, Z2.D

(661) 0x437bf8 ADD	X13, X13, #64

(661) 0x437bfc ADD	X9, X9, #64

(661) 0x437c00 LDR	Z2, [X13, MUL VL]

(661) 0x437c04 ADDVL	X12, SP, #8

(661) 0x437c08 ADDVL	X11, SP, #10

(661) 0x437c0c LDR	Z20, [X10, MUL VL]

(661) 0x437c10 ADDVL	X0, SP, #18

(661) 0x437c14 FMLA	Z20.D, P0/M, Z8.D, Z1.D

(661) 0x437c18 LDR	Z8, [X9, MUL VL]

(661) 0x437c1c FMUL	Z4.D, Z1.D, Z1.D

(661) 0x437c20 ADD	X12, X12, #64

(661) 0x437c24 FMLA	Z20.D, P0/M, Z8.D, Z4.D

(661) 0x437c28 ADD	X11, X11, #64

(661) 0x437c2c ADD	X0, X0, #64

(661) 0x437c30 LDR	Z22, [X12, MUL VL]

(661) 0x437c34 ADDVL	X4, SP, #17

(661) 0x437c38 FMLA	Z22.D, P0/M, Z2.D, Z1.D

(661) 0x437c3c ADDVL	X18, SP, #19

(661) 0x437c40 LDR	Z2, [X11, MUL VL]

(661) 0x437c44 LDR	Z8, [X0, MUL VL]

(661) 0x437c48 FMLA	Z22.D, P0/M, Z2.D, Z4.D

(661) 0x437c4c ADD	X4, X4, #64

(661) 0x437c50 ADD	X18, X18, #64

(661) 0x437c54 LDR	Z2, [X4, MUL VL]

(661) 0x437c58 ADDVL	X14, SP, #15

(661) 0x437c5c FMLA	Z2.D, P0/M, Z8.D, Z1.D

(661) 0x437c60 LDR	Z8, [X18, MUL VL]

(661) 0x437c64 FMUL	Z22.D, Z22.D, Z15.D

(661) 0x437c68 FMLA	Z2.D, P0/M, Z8.D, Z4.D

(661) 0x437c6c ADD	X14, X14, #64

(661) 0x437c70 ADDVL	X10, SP, #14

(661) 0x437c74 ADDVL	X12, SP, #16

(661) 0x437c78 LDR	Z8, [X14, MUL VL]

(661) 0x437c7c FMAD	Z20.D, P0/M, Z12.D, Z22.D

(661) 0x437c80 ADD	X10, X10, #64

(661) 0x437c84 ADD	X12, X12, #64

(661) 0x437c88 ADDVL	X9, SP, #12

(661) 0x437c8c LDR	Z22, [X10, MUL VL]

(661) 0x437c90 FMLA	Z22.D, P0/M, Z8.D, Z1.D

(661) 0x437c94 LDR	Z8, [X12, MUL VL]

(661) 0x437c98 FMLA	Z22.D, P0/M, Z8.D, Z4.D

(661) 0x437c9c FMUL	Z22.D, Z22.D, Z19.D

(661) 0x437ca0 FMAD	Z2.D, P0/M, Z16.D, Z22.D

(661) 0x437ca4 ADD	X9, X9, #64

(661) 0x437ca8 FADD	Z20.D, Z2.D, Z20.D

(661) 0x437cac ADDVL	X13, SP, #11

(661) 0x437cb0 FDUP	Z2.D, #112

(661) 0x437cb4 ADDVL	X4, SP, #9

(661) 0x437cb8 FDIVR	Z6.D, P0/M, Z6.D, Z2.D

(661) 0x437cbc ADDVL	X0, SP, #13

(661) 0x437cc0 FMUL	Z13.D, Z13.D, Z21.D

(661) 0x437cc4 FMUL	Z13.D, Z20.D, Z13.D

(661) 0x437cc8 ST1D	{Z13.D}, P2, [X6, Z17.D,LSL #3]

(661) 0x437ccc LDR	Z8, [X9, MUL VL]

(661) 0x437cd0 ADD	X13, X13, #64

(661) 0x437cd4 ADD	X4, X4, #64

(661) 0x437cd8 FMUL	Z13.D, Z6.D, Z21.D

(661) 0x437cdc ADD	X0, X0, #64

(661) 0x437ce0 ADDVL	X11, SP, #8

(661) 0x437ce4 LDR	Z6, [X13, MUL VL]

(661) 0x437ce8 ADDVL	X18, SP, #10

(661) 0x437cec FMLA	Z6.D, P0/M, Z8.D, Z0.D

(661) 0x437cf0 ADDVL	X14, SP, #18

(661) 0x437cf4 LDR	Z8, [X0, MUL VL]

(661) 0x437cf8 LDR	Z20, [X4, MUL VL]

(661) 0x437cfc FMUL	Z2.D, Z0.D, Z0.D

(661) 0x437d00 ADD	X11, X11, #64

(661) 0x437d04 FMLA	Z6.D, P0/M, Z8.D, Z2.D

(661) 0x437d08 ADD	X18, X18, #64

(661) 0x437d0c ADD	X14, X14, #64

(661) 0x437d10 ADDVL	X10, SP, #17

(661) 0x437d14 LDR	Z22, [X11, MUL VL]

(661) 0x437d18 ADDVL	X12, SP, #19

(661) 0x437d1c FMLA	Z22.D, P0/M, Z20.D, Z0.D

(661) 0x437d20 LDR	Z20, [X18, MUL VL]

(661) 0x437d24 LDR	Z8, [X14, MUL VL]

(661) 0x437d28 FMLA	Z22.D, P0/M, Z20.D, Z2.D

(661) 0x437d2c ADD	X10, X10, #64

(661) 0x437d30 ADD	X12, X12, #64

(661) 0x437d34 ADDVL	X9, SP, #15

(661) 0x437d38 LDR	Z20, [X10, MUL VL]

(661) 0x437d3c FMLA	Z20.D, P0/M, Z8.D, Z0.D

(661) 0x437d40 LDR	Z8, [X12, MUL VL]

(661) 0x437d44 FMUL	Z22.D, Z22.D, Z5.D

(661) 0x437d48 FMLA	Z20.D, P0/M, Z8.D, Z2.D

(661) 0x437d4c ADD	X9, X9, #64

(661) 0x437d50 ADDVL	X13, SP, #14

(661) 0x437d54 ADDVL	X11, SP, #16

(661) 0x437d58 LDR	Z8, [X9, MUL VL]

(661) 0x437d5c FMAD	Z6.D, P0/M, Z3.D, Z22.D

(661) 0x437d60 ADD	X13, X13, #64

(661) 0x437d64 ADD	X11, X11, #64

(661) 0x437d68 LDR	Z22, [X13, MUL VL]

(661) 0x437d6c FMLA	Z22.D, P0/M, Z8.D, Z0.D

(661) 0x437d70 LDR	Z8, [X11, MUL VL]

(661) 0x437d74 FMLA	Z22.D, P0/M, Z8.D, Z2.D

(661) 0x437d78 FMUL	Z22.D, Z22.D, Z7.D

(661) 0x437d7c ADD	X0, SP, #64

(661) 0x437d80 FMAD	Z20.D, P0/M, Z14.D, Z22.D

(661) 0x437d84 FADD	Z6.D, Z6.D, Z20.D

(661) 0x437d88 FMUL	Z13.D, Z6.D, Z13.D

(661) 0x437d8c ST1D	{Z13.D}, P1, [X6, Z18.D,LSL #3]

(661) 0x437d90 LDR	Z22, [X0, #2, MUL VL]

(661) 0x437d94 ADDVL	X4, SP, #22

(661) 0x437d98 LDR	Z6, [X0, MUL VL]

(661) 0x437d9c FMLA	Z6.D, P0/M, Z22.D, Z1.D

(661) 0x437da0 LDR	Z22, [X0, #3, MUL VL]

(661) 0x437da4 FMUL	Z20.D, Z4.D, Z1.D

(661) 0x437da8 ADD	X4, X4, #64

(661) 0x437dac LDR	Z8, [X4, MUL VL]

(661) 0x437db0 FMUL	Z13.D, Z8.D, Z4.D

(661) 0x437db4 FMLA	Z13.D, P0/M, Z22.D, Z20.D

(661) 0x437db8 LDR	Z22, [X0, #6, MUL VL]

(661) 0x437dbc FADD	Z13.D, Z13.D, Z6.D

(661) 0x437dc0 FMUL	Z22.D, Z22.D, Z4.D

(661) 0x437dc4 LDR	Z6, [X0, #7, MUL VL]

(661) 0x437dc8 FMUL	Z13.D, Z13.D, Z19.D

(661) 0x437dcc FMLA	Z22.D, P0/M, Z6.D, Z20.D

(661) 0x437dd0 LDR	Z19, [X0, #5, MUL VL]

(661) 0x437dd4 LDR	Z6, [X0, #4, MUL VL]

(661) 0x437dd8 ADD	X10, SP, #64

(661) 0x437ddc FMLA	Z6.D, P0/M, Z19.D, Z1.D

(661) 0x437de0 ADDVL	X18, X0, #23

(661) 0x437de4 FMUL	Z19.D, Z4.D, Z26.D

(661) 0x437de8 FADD	Z6.D, Z6.D, Z22.D

(661) 0x437dec FMLA	Z19.D, P0/M, Z20.D, Z27.D

(661) 0x437df0 FMAD	Z6.D, P0/M, Z16.D, Z13.D

(661) 0x437df4 LDR	Z22, [X10, #1, MUL VL]

(661) 0x437df8 MOVPRFX	Z13, Z24

(661) 0x437dfc FMLA	Z13.D, P0/M, Z1.D, Z25.D

(661) 0x437e00 ADDVL	X12, SP, #21

(661) 0x437e04 FADD	Z13.D, Z13.D, Z19.D

(661) 0x437e08 LDR	Z16, [X18, MUL VL]

(661) 0x437e0c FMUL	Z4.D, Z4.D, Z16.D

(661) 0x437e10 FMAD	Z20.D, P0/M, Z22.D, Z4.D

(661) 0x437e14 ADD	X13, SP, #64

(661) 0x437e18 FMUL	Z15.D, Z13.D, Z15.D

(661) 0x437e1c ADDVL	X14, X10, #20

(661) 0x437e20 ADD	X12, X12, #64

(661) 0x437e24 ADDVL	X11, SP, #21

(661) 0x437e28 LDR	Z4, [X14, MUL VL]

(661) 0x437e2c LDR	Z19, [X12, MUL VL]

(661) 0x437e30 FMAD	Z1.D, P0/M, Z4.D, Z19.D

(661) 0x437e34 FADD	Z1.D, Z1.D, Z20.D

(661) 0x437e38 FMUL	Z20.D, Z8.D, Z2.D

(661) 0x437e3c FMAD	Z12.D, P0/M, Z1.D, Z15.D

(661) 0x437e40 FADD	Z12.D, Z6.D, Z12.D

(661) 0x437e44 ST1D	{Z12.D}, P2, [X5, Z17.D,LSL #3]

(661) 0x437e48 FMUL	Z17.D, Z2.D, Z0.D

(661) 0x437e4c LDR	Z6, [X13, #2, MUL VL]

(661) 0x437e50 LDR	Z22, [X13, #3, MUL VL]

(661) 0x437e54 LDR	Z13, [X13, #6, MUL VL]

(661) 0x437e58 FMLA	Z20.D, P0/M, Z22.D, Z17.D

(661) 0x437e5c LDR	Z8, [X13, MUL VL]

(661) 0x437e60 FMLA	Z8.D, P0/M, Z6.D, Z0.D

(661) 0x437e64 FMUL	Z4.D, Z13.D, Z2.D

(661) 0x437e68 FADD	Z19.D, Z8.D, Z20.D

(661) 0x437e6c LDR	Z15, [X13, #7, MUL VL]

(661) 0x437e70 FMUL	Z1.D, Z19.D, Z7.D

(661) 0x437e74 FMLA	Z4.D, P0/M, Z15.D, Z17.D

(661) 0x437e78 LDR	Z7, [X13, #4, MUL VL]

(661) 0x437e7c LDR	Z12, [X13, #5, MUL VL]

(661) 0x437e80 FMUL	Z20.D, Z2.D, Z26.D

(661) 0x437e84 FMLA	Z7.D, P0/M, Z12.D, Z0.D

(661) 0x437e88 FMLA	Z20.D, P0/M, Z17.D, Z27.D

(661) 0x437e8c ADDVL	X9, X13, #20

(661) 0x437e90 ADD	X11, X11, #64

(661) 0x437e94 FADD	Z8.D, Z7.D, Z4.D

(661) 0x437e98 FMAD	Z8.D, P0/M, Z14.D, Z1.D

(661) 0x437e9c FMUL	Z14.D, Z2.D, Z16.D

(661) 0x437ea0 MOVPRFX	Z2, Z24

(661) 0x437ea4 FMLA	Z2.D, P0/M, Z0.D, Z25.D

(661) 0x437ea8 LDR	Z16, [X13, #1, MUL VL]

(661) 0x437eac FADD	Z6.D, Z2.D, Z20.D

(661) 0x437eb0 FMAD	Z17.D, P0/M, Z16.D, Z14.D

(661) 0x437eb4 FMUL	Z5.D, Z5.D, Z6.D

(661) 0x437eb8 LDR	Z22, [X9, MUL VL]

(661) 0x437ebc LDR	Z13, [X11, MUL VL]

(661) 0x437ec0 FMAD	Z0.D, P0/M, Z22.D, Z13.D

(661) 0x437ec4 FADD	Z0.D, Z0.D, Z17.D

(661) 0x437ec8 FMAD	Z3.D, P0/M, Z0.D, Z5.D

(661) 0x437ecc FADD	Z3.D, Z3.D, Z8.D

(661) 0x437ed0 ST1D	{Z3.D}, P1, [X5, Z18.D,LSL #3]

(661) 0x437ed4 ADD	X2, X2, X3

(661) 0x437ed8 WHILELO	P3.S, W2, W8

(661) 0x437edc B.NE	437aac

0x437ee0 LDP	D8, D9, [SP]

0x437ee4 LDP	D10, D11, [SP, #16]

0x437ee8 LDP	D12, D13, [SP, #32]

0x437eec LDP	D14, D15, [SP, #48]

(662) 0x437ef0 ADDVL	SP, SP, #25

(662) 0x437ef4 ADD	SP, SP, #64

(662) 0x437ef8 RET

(662) 0x437efc ADD	W11, W2, W4

(662) 0x437f00 CMP	W11, W1

(662) 0x437f04 B.EQ	43772c

(662) 0x437f08 STR	W4, [X16, X8,SXTW #2]

(662) 0x437f0c STR	D5, [X15, X8,SXTW #3]

(662) 0x437f10 ADD	W8, W8, #1

(662) 0x437f14 B	43772c

0x437f18 ADD	W13, W2, W4

0x437f1c CMP	W13, W1

0x437f20 B.EQ	4376f4

0x437f24 STR	W4, [X16, X8,SXTW #2]

0x437f28 STR	D3, [X15, X8,SXTW #3]

0x437f2c ADD	W8, W8, #1

0x437f30 B	4376f4

0x437f34 HINT	#0

0x437f38 HINT	#0

0x437f3c HINT	#0

Coverage (%)	Name	Source Location	Module
►50.00+	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1168	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1168	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►25.00+	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1168	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:207	exec
○	main._omp_fn.1	stl_vector.h:1043	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	BsplineFunctor.h:266-339
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:266,276,283-284,291-298,305-339
/usr/include/c++/11/bits/stl_vector.h:1061

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 36.50 to 34.50 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 46% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 36.50 to 22.50 cycles (1.62x speedup).

Details

34% of VPU instructions are used in vector version (process two or more data elements in vector registers):

8% of VPU loads are used in vector version.
87% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 432 bytes. The binary function is storing 912 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	193
loop length	772
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	18.00	18.00	24.00	18.00	10.25	10.25	10.25	10.25	36.50	36.50	13.00	2.00	2.00
cycles	9.00	9.00	18.00	18.00	24.00	18.00	10.25	10.25	10.25	10.25	36.50	36.50	13.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.75
Overall L1	36.50

Vectorization ratios

all	34%
load	8%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.50 cycles. At this rate:

12% of peak load performance is reached (11.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
52% of peak store performance is reached (24.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 437600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CNTB X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X13, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X12, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X8, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB SP, SP, X9,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D21, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADDVL X10, SP, #25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W3, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X10, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMUL D23, D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437ef0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X17, X2, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W14, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D0, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X18, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 437788 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437758 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437730 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437720 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376f8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376c0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 4376bc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376bc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D1, [X15, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
MOVZ X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 4376e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D2, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 437f18 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 43771c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43771c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D4, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 437efc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL X1, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X18, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D8, D9, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADDVL X10, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X14, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D10, D11, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADDVL X13, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X11, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D12, D13, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X1, X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D14, D15, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X10, X10, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X13, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z12.D}, P0/Z, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X12, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z13.D}, P0/Z, [X0, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X4, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z27.D}, P0/Z, [X0, #26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z14.D}, P0/Z, [X0, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z15.D}, P0/Z, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z1.D}, P0/Z, [X0, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X12, X12, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z12, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X1, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z13, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X18, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z27, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X13, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z14, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X10, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z15, [X14, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X14, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z1, [X11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X11, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z26.D}, P0/Z, [X0, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z8.D}, P0/Z, [X0, #42]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z0.D}, P0/Z, [X0, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X1, X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z11.D}, P0/Z, [X0, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z10.D}, P0/Z, [X0, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z9.D}, P0/Z, [X0, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z31.D}, P0/Z, [X0, #45]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z30.D}, P0/Z, [X0, #46]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z29.D}, P0/Z, [X0, #49]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #50]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X7, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z26, [X12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X10, X10, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X12, X14, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z0, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z2.D}, P0/Z, [X0, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X9, X13, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z24.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z25.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z3.D}, P0/Z, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z4.D}, P0/Z, [X0, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z5.D}, P0/Z, [X0, #34]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z6.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z7.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z16.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z17.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z19.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z20.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z22.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z12.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
STR Z24, [X13, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z6, [X14, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z7, [X14, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z16, [X14, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z17, [X14, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z18, [X14, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z20, [X13, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z2, [X4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
CNTW X3, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X4, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z3, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z25, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z4, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z5, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z19, [X12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z22, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z12, [X11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LD1RD {Z13.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X4, X4, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR Z13, [X4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z26.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z25.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z24.D}, P0/Z, [X0, #18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X0, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z21.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z23.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
WHILELO P3.S, WZR, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
STR Z8, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDP D8, D9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D12, D13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D14, D15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W13, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376f4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D3, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4376f4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	BsplineFunctor.h:266-339
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:266,276,283-284,291-298,305-339
/usr/include/c++/11/bits/stl_vector.h:1061

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

34% of VPU instructions are used in vector version (process two or more data elements in vector registers):

8% of VPU loads are used in vector version.
87% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 432 bytes. The binary function is storing 912 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	193
loop length	772
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.00	9.00	18.00	18.00	24.00	18.00	10.25	10.25	10.25	10.25	36.50	36.50	13.00	2.00	2.00
cycles	9.00	9.00	18.00	18.00	24.00	18.00	10.25	10.25	10.25	10.25	36.50	36.50	13.00	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.75
Overall L1	36.50

Vectorization ratios

all	34%
load	8%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.50 cycles. At this rate:

12% of peak load performance is reached (11.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
52% of peak store performance is reached (24.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 437600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CNTB X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X13, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X12, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X8, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB SP, SP, X9,UXTX	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D21, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADDVL X10, SP, #25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W3, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X10, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMUL D23, D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437ef0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X17, X2, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS W14, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D0, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X18, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 437788 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437758 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437730 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 437720 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376f8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376c0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 4376bc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376bc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D1, [X15, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
MOVZ X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 4376e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376e4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D2, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 437f18 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 43771c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W9, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43771c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D4, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D0, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 437efc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL X1, SP, #19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X18, SP, #18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D8, D9, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADDVL X10, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X14, SP, #16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D10, D11, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADDVL X13, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X11, SP, #12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP D12, D13, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X1, X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D14, D15, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X10, X10, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X13, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z12.D}, P0/Z, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X12, SP, #15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X9, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z13.D}, P0/Z, [X0, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X4, SP, #11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z27.D}, P0/Z, [X0, #26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z14.D}, P0/Z, [X0, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z15.D}, P0/Z, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z1.D}, P0/Z, [X0, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X12, X12, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z12, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X1, SP, #10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z13, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X18, SP, #9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z27, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X13, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z14, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X10, SP, #8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z15, [X14, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X14, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z1, [X11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADDVL X11, SP, #20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z26.D}, P0/Z, [X0, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z8.D}, P0/Z, [X0, #42]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z0.D}, P0/Z, [X0, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X1, X1, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z11.D}, P0/Z, [X0, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z10.D}, P0/Z, [X0, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z9.D}, P0/Z, [X0, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z31.D}, P0/Z, [X0, #45]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z30.D}, P0/Z, [X0, #46]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z29.D}, P0/Z, [X0, #49]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #50]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X7, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z26, [X12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X10, X10, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X12, X14, #22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z0, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z2.D}, P0/Z, [X0, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X9, X13, #23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z24.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z25.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z3.D}, P0/Z, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z4.D}, P0/Z, [X0, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z5.D}, P0/Z, [X0, #34]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z6.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z7.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z16.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z17.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z19.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z20.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z22.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z12.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
STR Z24, [X13, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z6, [X14, #7, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z7, [X14, #6, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z16, [X14, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z17, [X14, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z18, [X14, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z20, [X13, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X17, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z2, [X4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
CNTW X3, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X4, SP, #21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z3, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z25, [X9, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z4, [X18, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z5, [X10, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z19, [X12, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z22, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STR Z12, [X11, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LD1RD {Z13.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADD X4, X4, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR Z13, [X4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z26.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z25.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z24.D}, P0/Z, [X0, #18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADDVL X0, SP, #24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z21.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z23.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
WHILELO P3.S, WZR, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
STR Z8, [X0, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDP D8, D9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D12, D13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D14, D15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W13, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4376f4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W4, [X16, X8,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D3, [X15, X8,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4376f4 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const–	0.03	0.02
○Loop 661 - BsplineFunctor.h:305-336 - exec	0	0
○Loop 664 - BsplineFunctor.h:266-266 - exec	0	0
▼Loop 662 - BsplineFunctor.h:291-339 - exec–	0	0
○Loop 663 - BsplineFunctor.h:291-297 - exec	0.02	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code