OV - exec - Loop 900

0x44eae0 ORR	X11, XZR, X4

0x44eae4 LDR	D29, [X0, X21,LSL #3]    [6]

0x44eae8 ADD	X10, X21, #1

0x44eaec ADD	X26, X21, #2

0x44eaf0 ADD	X8, X21, #3

0x44eaf4 LDP	D0, D5, [X4, #8]    [8]

0x44eaf8 ADD	X21, X21, #4

0x44eafc LDR	D30, [X11], #24    [4]

0x44eb00 FMADD	D2, D0, D29, D26

0x44eb04 FMADD	D1, D29, D5, D27

0x44eb08 FMADD	D31, D30, D29, D28

0x44eb0c STR	D1, [X19, #16]    [7]

0x44eb10 STP	D31, D2, [X19]    [7]

0x44eb14 LDR	D3, [X0, X10,LSL #3]    [1]

0x44eb18 LDP	D6, D16, [X11, #8]    [4]

0x44eb1c LDR	D4, [X4, #24]    [8]

0x44eb20 FMADD	D17, D6, D3, D2

0x44eb24 FMADD	D18, D3, D16, D1

0x44eb28 FMADD	D7, D4, D3, D31

0x44eb2c STR	D18, [X19, #16]    [7]

0x44eb30 STP	D7, D17, [X19]    [7]

0x44eb34 LDR	D19, [X0, X26,LSL #3]    [5]

0x44eb38 LDP	D20, D21, [X4, #48]    [8]

0x44eb3c LDR	D22, [X4, #64]    [8]

0x44eb40 FMADD	D26, D21, D19, D17

0x44eb44 FMADD	D28, D20, D19, D7

0x44eb48 FMADD	D27, D19, D22, D18

0x44eb4c STP	D28, D26, [X19]    [7]

0x44eb50 STR	D27, [X19, #16]    [7]

0x44eb54 LDR	D22, [X0, X8,LSL #3]    [2]

0x44eb58 LDP	D25, D23, [X4, #72]    [8]

0x44eb5c ADD	X4, X4, #96

0x44eb60 LDUR	D24, [X4, #504]    [3]

0x44eb64 FMADD	D26, D23, D22, D26

0x44eb68 FMADD	D28, D25, D22, D28

0x44eb6c FMADD	D27, D22, D24, D27

0x44eb70 STP	D28, D26, [X19]    [7]

0x44eb74 STR	D27, [X19, #16]    [7]

0x44eb78 CMP	W5, W21

0x44eb7c B.GT	44eae0

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 154 - 154

--------------------------------------------------------------------------------

154:   for (int i = 0; i < n; i++)

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:918	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source	inner_product.hpp:154-154,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.40
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.00
Vectorization ratio load	33.33
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.00
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source	inner_product.hpp:154-154,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.40
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.00
Vectorization ratio load	33.33
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.00
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.40 cycles (3.33x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	5.00	5.00	5.00	5.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	2.00	2.00	2.00	2.00	5.00	5.00	5.00	5.00	6.67	6.67	6.67	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	40%
load	33%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44eae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X21, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D0, D5, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X21, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D30, [X11], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D1, D29, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D31, D30, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D1, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D31, D2, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X0, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D6, D16, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D17, D6, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D18, D3, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D7, D4, D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D18, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D7, D17, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D19, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D20, D21, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D21, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D20, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D19, D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D28, D26, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR D27, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D22, [X0, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D25, D23, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D24, [X4, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D23, D22, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D25, D22, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D22, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D28, D26, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR D27, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 44eae0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.40 cycles (3.33x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	5.00	5.00	5.00	5.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	2.00	2.00	2.00	2.00	5.00	5.00	5.00	5.00	6.67	6.67	6.67	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	40%
load	33%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44eae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X26, X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X21, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D0, D5, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X21, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D30, [X11], #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D1, D29, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D31, D30, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D1, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D31, D2, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X0, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D6, D16, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D17, D6, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D18, D3, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D7, D4, D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D18, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STP D7, D17, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D19, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D20, D21, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D21, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D20, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D19, D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D28, D26, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR D27, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D22, [X0, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D25, D23, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D24, [X4, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D23, D22, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D25, D22, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D27, D22, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D28, D26, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR D27, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 44eae0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code