OV - exec - Loop 899

0x44eb80 LDR	X0, [X20, #1096]    [5]

0x44eb84 ADRP	X20,

0x44eb88 BL	47a180

0x44eb8c LDR	X0, [X20, #4016]    [4]

0x44eb90 LDR	X2, [SP, #280]    [2]

0x44eb94 LDR	X1, [X0]    [1]

0x44eb98 SUBS	X2, X2, X1

0x44eb9c MOVZ	X1, #0

0x44eba0 B.NE	44ec08

0x44eba4 ORR	X0, XZR, X19

0x44eba8 LDP	X29, X30, [SP, #32]    [2]

0x44ebac LDP	X19, X20, [SP, #48]    [2]

0x44ebb0 LDP	X21, X22, [SP, #64]    [2]

0x44ebb4 LDP	X25, X26, [SP, #96]    [2]

0x44ebb8 ADD	SP, SP, #288

0x44ebbc RET

0x44ebc0 LDR	X1, [X20, #1040]    [3]

0x44ebc4 LDR	X0, [X20, #1056]    [3]

0x44ebc8 CBZ	X1, 44ebfc

0x44ebfc STP	XZR, XZR, [X19]    [6]

0x44ec00 STR	XZR, [X19, #16]    [6]

0x44ec04 B	44eb80

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 154 - 154

--------------------------------------------------------------------------------

154:   for (int i = 0; i < n; i++)

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183

--------------------------------------------------------------------------------

183:     return (const_cast<T1&>(a) = b);

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 89 - 91

--------------------------------------------------------------------------------

89:   RatioTimer->stop();

90:   return g;

91: }

/usr/include/c++/11/bits/stl_algo.h: 751 - 751

--------------------------------------------------------------------------------

751:       if (__n2 <= 0)

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:189	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source	inner_product.hpp:154-154,OperatorTags.h:183-183,DiracDeterminantRef.cpp:89-91,stl_algo.h:751-751
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11, P12,
Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source	inner_product.hpp:154-154,OperatorTags.h:183-183,DiracDeterminantRef.cpp:89-91,stl_algo.h:751-751
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:89-91
/usr/include/c++/11/bits/stl_algo.h:751

The related source loop is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00
cycles	2.50	2.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

29% of peak load performance is reached (28.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44eb80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [X20, #1096]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X20, <4c1b84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X0, [X20, #4016]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.NE 44ec08 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #1040]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #1056]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X1, 44ebfc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, XZR, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44eb80 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:183
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:89-91
/usr/include/c++/11/bits/stl_algo.h:751

The related source loop is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00
cycles	2.50	2.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

29% of peak load performance is reached (28.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44eb80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [X20, #1096]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X20, <4c1b84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 47a180 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X0, [X20, #4016]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.NE 44ec08 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #1040]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X20, #1056]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X1, 44ebfc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, XZR, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44eb80 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code