OV - exec - Loop 758

0x43ea98 LDR	W0, [X26, #64]    [3]

0x43ea9c MADD	W15, W10, W19, WZR

0x43eaa0 ADD	W19, W19, #1

0x43eaa4 LDR	W25, [X26, #8]    [3]

0x43eaa8 MADD	W1, W19, W0, WZR

0x43eaac CMP	W1, W25

0x43eab0 CSEL	W2, W1, W25, #13

0x43eab4 SUB	W5, W2, W15

0x43eab8 CMP	W5, #0

0x43eabc B.LE	43eae0

0x43eac0 LDR	X8, [SP, #208]    [1]

0x43eac4 SBFM	X2, X5, #61, #31

0x43eac8 LDR	X7, [X26, #768]    [3]

0x43eacc LDR	X9, [X8, #24]    [2]

0x43ead0 ADD	X0, X9, W15,SXTW #3

0x43ead4 LDR	X1, [X7, X20]    [4]

0x43ead8 BL	4036e0

0x43eadc LDR	W10, [X26, #48]    [3]

0x43eae0 ADD	X20, X20, #24

0x43eae4 CMP	W19, W10

0x43eae8 B.LT	43ea98

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 183 - 187

--------------------------------------------------------------------------------

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

/usr/include/c++/11/bits/stl_algobase.h: 431 - 431

--------------------------------------------------------------------------------

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/usr/include/c++/11/bits/stl_vector.h: 1169 - 1169

--------------------------------------------------------------------------------

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/include/c++/11/bits/stl_algo.h: 751 - 751

--------------------------------------------------------------------------------

751:       if (__n2 <= 0)

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:194	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:214	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.30
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:431-431,stl_vector.h:1169-1169,stl_algo.h:751-751
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.63
CQA cycles if no scalar integer	2.63
CQA cycles if FP arith vectorized	2.63
CQA cycles if fully vectorized	0.36
Front-end cycles	2.13
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	2.63
P2 cycles	2.63
P3 cycles	2.63
P4 cycles	2.63
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.11
Bytes prefetched	0.00
Bytes loaded	26.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:431-431,stl_vector.h:1169-1169,stl_algo.h:751-751
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.41
Front-end cycles	2.63
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.67
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	einspline_spo_ref.hpp:183-187,stl_algobase.h:431-431,stl_vector.h:1169-1169,stl_algo.h:751-751
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.31
Front-end cycles	1.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.56
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/usr/include/c++/11/bits/stl_algobase.h:431
/usr/include/c++/11/bits/stl_vector.h:1169
/usr/include/c++/11/bits/stl_algo.h:751

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.63 to 0.36 cycles (7.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.63 to 1.00 cycles (2.62x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 26 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.25	1.25	2.63	2.63	2.63	2.63	0.00	0.00	0.00	0.00	1.50	1.50	1.50	0.00	0.00
cycles	1.25	1.25	2.63	2.63	2.63	2.63	0.00	0.00	0.00	0.00	1.50	1.50	1.50	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.13
Data deps.	1.00
Overall L1	2.63

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.63 cycles. At this rate:

9% of peak load performance is reached (9.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/usr/include/c++/11/bits/stl_algobase.h:431
/usr/include/c++/11/bits/stl_vector.h:1169
/usr/include/c++/11/bits/stl_algo.h:751

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 44 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.63
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

15% of peak load performance is reached (14.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43ea98

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR W0, [X26, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W15, W10, W19, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W25, [X26, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W1, W19, W0, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W1, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W2, W1, W25, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W5, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 43eae0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X2, X5, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X26, #768]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X8, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X9, W15,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
LDR X1, [X7, X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 4036e0 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W10, [X26, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X20, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 43ea98 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/usr/include/c++/11/bits/stl_algobase.h:431
/usr/include/c++/11/bits/stl_vector.h:1169
/usr/include/c++/11/bits/stl_algo.h:751

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.31 cycles (7.20x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43ea98

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR W0, [X26, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W15, W10, W19, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD W19, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W25, [X26, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W1, W19, W0, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W1, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W2, W1, W25, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W5, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 43eae0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X20, X20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 43ea98 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code