OV - exec - Loop 51

	Loop Id: 51	Module: exec	Source: random.tcc:401-3369 [...]	Coverage: 0.6%

0x406ae0 FDIV	D16, D6, D7

0x406ae4 FMOV	D17, #1.0000000

0x406ae8 MOVN	X8, #49168

0x406aec LDP	D30, D20, [X27, #920]

0x406af0 MOVZ	X6, #16880

0x406af4 MOVI	D23, #0

0x406af8 FMOV	D18, X8

0x406afc MOVZ	W10, #2

0x406b00 ADD	X9, X22, #1832

0x406b04 ADD	X8, X22, #3184

0x406b08 MOVZ	X11, #61382

0x406b0c FMOV	D1, X6

0x406b10 FMOV	D3, D17

0x406b14 FSUB	D31, D20, S30

0x406b18 FCMPE	D16, D17

0x406b1c FCSEL	D19, D16, D18, #4

0x406b20 FMADD	D21, D31, D19, D30

0x406b24 FMSUB	D0, D21, D9, D17

0x406b28 CMP	X24, #624

0x406b2c B.EQ	406efc

    (49) 0x406b30 ORR	X6, XZR, X24

    (49) 0x406b34 ADD	X24, X24, #1

    (49) 0x406b38 LDR	X18, [X26, X6,LSL #3]

    (49) 0x406b3c STR	X24, [X26, #4992]

    (49) 0x406b40 UBFM	X17, X18, #11, #42

    (49) 0x406b44 EOR	X7, X18, X17

    (49) 0x406b48 AND	X15, X3, X7,LSL #7

    (49) 0x406b4c EOR	X4, X7, X15

    (49) 0x406b50 AND	X30, X11, X4,LSL #15

    (49) 0x406b54 EOR	X13, X4, X30

    (49) 0x406b58 EOR	X12, X13, X13,LSR #18

    (49) 0x406b5c UCVTF	D22, X12

    (49) 0x406b60 FMADD	D23, D22, D3, D23

    (49) 0x406b64 FMUL	D3, D3, D1

    (49) 0x406b68 CMP	W10, #1

    (49) 0x406b6c B.NE	406ef0

0x406b70 FDIV	D24, D23, D3

0x406b74 FMOV	D25, #1.0000000

0x406b78 MOVN	X10, #49168

0x406b7c FMOV	D26, X10

0x406b80 FCMPE	D24, D25

0x406b84 FCSEL	D27, D24, D26, #4

0x406b88 FMADD	D14, D31, D27, D30

0x406b8c BL	403740

0x406b90 FMOV	D28, #-2.0000000

0x406b94 ORR	X1, XZR, X20

0x406b98 ORR	X0, XZR, X21

0x406b9c FMUL	D29, D0, D28

0x406ba0 FMUL	D0, D14, D8

0x406ba4 FSQRT	D13, D29

0x406ba8 BL	403c30

0x406bac LDP	D30, D31, [SP, #400]

0x406bb0 MOVZ	X3, #22144

0x406bb4 MOVK	X3, #40236

0x406bb8 FMUL	D4, D30, D13

0x406bbc FMUL	D0, D31, D13

0x406bc0 STP	D4, D0, [X23]

0x406bc4 ADD	X23, X23, #16

0x406bc8 CMP	X19, X23

0x406bcc B.EQ	4071b0

0x406bd0 MOVZ	X11, #16880

0x406bd4 MOVI	D6, #0

0x406bd8 FMOV	D7, #1.0000000

0x406bdc MOVZ	W10, #2

0x406be0 ADD	X9, X22, #1832

0x406be4 FMOV	D18, X11

0x406be8 ADD	X8, X22, #3184

0x406bec MOVZ	X11, #61382

0x406bf0 CMP	X24, #623

0x406bf4 B.HI	406c44

  (52) 0x406bf8 ORR	X6, XZR, X24

  (52) 0x406bfc ADD	X24, X24, #1

  (52) 0x406c00 LDR	X18, [X26, X6,LSL #3]

  (52) 0x406c04 STR	X24, [X26, #4992]

  (52) 0x406c08 UBFM	X17, X18, #11, #42

  (52) 0x406c0c EOR	X15, X18, X17

  (52) 0x406c10 AND	X30, X3, X15,LSL #7

  (52) 0x406c14 EOR	X0, X15, X30

  (52) 0x406c18 AND	X13, X11, X0,LSL #15

  (52) 0x406c1c EOR	X2, X0, X13

  (52) 0x406c20 EOR	X12, X2, X2,LSR #18

  (52) 0x406c24 UCVTF	D5, X12

  (52) 0x406c28 FMADD	D6, D5, D7, D6

  (52) 0x406c2c FMUL	D7, D7, D18

  (52) 0x406c30 CMP	W10, #1

  (52) 0x406c34 B.EQ	406ae0

  (52) 0x406c38 MOVZ	W10, #1

  (52) 0x406c3c CMP	X24, #623

  (52) 0x406c40 B.LS	406bf8

  (53) 0x406c44 SUB	X24, X9, X26

  (53) 0x406c48 ORR	X1, XZR, X26

  (53) 0x406c4c SUB	X4, X24, #8

  (53) 0x406c50 ORR	X17, XZR, X26

  (53) 0x406c54 UBFM	X16, X4, #3, #63

  (53) 0x406c58 ADD	X14, X16, #1

  (53) 0x406c5c ANDS	X18, X14, #4160

  (53) 0x406c60 B.EQ	406ce0

0x406c64 CMP	X18, #1

0x406c68 B.EQ	406cb4

0x406c6c CMP	X18, #2

0x406c70 B.EQ	406c94

0x406c74 LDP	X30, X0, [X26]

0x406c78 LDR	X13, [X26, #3176]

0x406c7c BFM	X30, X0, #0, #30

0x406c80 ANDS	XZR, X30, #4096

0x406c84 EOR	X2, X13, X30,LSR #1

0x406c88 EOR	X12, X2, X25

0x406c8c CSEL	X15, X12, X2, #1

0x406c90 STR	X15, [X17], #8

0x406c94 LDP	X7, X5, [X17]

0x406c98 LDR	X6, [X17, #3176]

0x406c9c BFM	X7, X5, #0, #30

0x406ca0 ANDS	XZR, X7, #4096

0x406ca4 EOR	X24, X6, X7,LSR #1

0x406ca8 EOR	X4, X24, X25

0x406cac CSEL	X16, X4, X24, #1

0x406cb0 STR	X16, [X17], #8

0x406cb4 LDP	X14, X18, [X17]

0x406cb8 LDR	X30, [X17, #3176]

0x406cbc BFM	X14, X18, #0, #30

0x406cc0 ANDS	XZR, X14, #4096

0x406cc4 EOR	X0, X30, X14,LSR #1

0x406cc8 EOR	X13, X0, X25

0x406ccc CSEL	X2, X13, X0, #1

0x406cd0 STR	X2, [X17], #8

0x406cd4 CMP	X9, X17

0x406cd8 B.EQ	406d74

0x406cdc HINT	#0

  (45) 0x406ce0 LDP	X12, X7, [X17]

  (45) 0x406ce4 ORR	X15, XZR, X17

  (45) 0x406ce8 LDR	X5, [X17, #3176]

  (45) 0x406cec BFM	X12, X7, #0, #30

  (45) 0x406cf0 ANDS	XZR, X12, #4096

  (45) 0x406cf4 EOR	X6, X5, X12,LSR #1

  (45) 0x406cf8 EOR	X24, X6, X25

  (45) 0x406cfc CSEL	X4, X24, X6, #1

  (45) 0x406d00 STR	X4, [X15], #8

  (45) 0x406d04 LDR	X16, [X15, #8]

  (45) 0x406d08 LDR	X14, [X15, #3176]

  (45) 0x406d0c BFM	X7, X16, #0, #30

  (45) 0x406d10 ORR	X13, XZR, X16

  (45) 0x406d14 EOR	X18, X14, X7,LSR #1

  (45) 0x406d18 ANDS	XZR, X7, #4096

  (45) 0x406d1c EOR	X30, X18, X25

  (45) 0x406d20 CSEL	X0, X30, X18, #1

  (45) 0x406d24 STR	X0, [X17, #8]

  (45) 0x406d28 LDR	X2, [X15, #16]

  (45) 0x406d2c LDR	X12, [X15, #3184]

  (45) 0x406d30 BFM	X13, X2, #0, #30

  (45) 0x406d34 EOR	X6, X12, X13,LSR #1

  (45) 0x406d38 ANDS	XZR, X13, #4096

  (45) 0x406d3c EOR	X5, X6, X25

  (45) 0x406d40 CSEL	X24, X5, X6, #1

  (45) 0x406d44 STR	X24, [X15, #8]

  (45) 0x406d48 LDP	X15, X4, [X17, #24]

  (45) 0x406d4c ADD	X17, X17, #32

  (45) 0x406d50 LDR	X7, [X17, #3168]

  (45) 0x406d54 BFM	X15, X4, #0, #30

  (45) 0x406d58 ANDS	XZR, X15, #4096

  (45) 0x406d5c EOR	X16, X7, X15,LSR #1

  (45) 0x406d60 EOR	X14, X16, X25

  (45) 0x406d64 CSEL	X18, X14, X16, #1

  (45) 0x406d68 STUR	X18, [X17, #504]

  (45) 0x406d6c CMP	X9, X17

  (45) 0x406d70 B.NE	406ce0

0x406d74 SUB	X17, X8, X26

0x406d78 SUB	X30, X17, #8

0x406d7c UBFM	X0, X30, #3, #63

0x406d80 ADD	X13, X0, #1

0x406d84 ANDS	X2, X13, #4160

0x406d88 B.EQ	406e20

0x406d8c CMP	X2, #1

0x406d90 B.EQ	406dec

0x406d94 CMP	X2, #2

0x406d98 B.EQ	406dc4

0x406d9c LDR	X6, [X26, #1816]

0x406da0 ADD	X1, X26, #8

0x406da4 LDR	X5, [X26, #1824]

0x406da8 LDR	X12, [X26]

0x406dac BFM	X6, X5, #0, #30

0x406db0 EOR	X24, X12, X6,LSR #1

0x406db4 ANDS	XZR, X6, #4096

0x406db8 EOR	X15, X24, X25

0x406dbc CSEL	X4, X15, X24, #1

0x406dc0 STR	X4, [X26, #1816]

0x406dc4 LDR	X16, [X1, #1816]

0x406dc8 ADD	X1, X1, #8

0x406dcc LDR	X14, [X1, #1816]

0x406dd0 LDUR	X7, [X1, #504]

0x406dd4 BFM	X16, X14, #0, #30

0x406dd8 EOR	X18, X7, X16,LSR #1

0x406ddc ANDS	XZR, X16, #4096

0x406de0 EOR	X17, X18, X25

0x406de4 CSEL	X30, X17, X18, #1

0x406de8 STR	X30, [X1, #1808]

0x406dec LDR	X13, [X1, #1816]

0x406df0 ADD	X1, X1, #8

0x406df4 LDR	X2, [X1, #1816]

0x406df8 LDUR	X0, [X1, #504]

0x406dfc BFM	X13, X2, #0, #30

0x406e00 EOR	X12, X0, X13,LSR #1

0x406e04 ANDS	XZR, X13, #4096

0x406e08 EOR	X6, X12, X25

0x406e0c CSEL	X5, X6, X12, #1

0x406e10 STR	X5, [X1, #1808]

0x406e14 CMP	X8, X1

0x406e18 B.EQ	406ec0

0x406e1c HINT	#0

  (46) 0x406e20 ADD	X16, X1, #1816

  (46) 0x406e24 LDR	X7, [X1]

  (46) 0x406e28 ADD	X15, X1, #16

  (46) 0x406e2c LDP	X14, X4, [X16]

  (46) 0x406e30 ADD	X24, X1, #24

  (46) 0x406e34 ADD	X1, X1, #32

  (46) 0x406e38 LDP	X18, X17, [X16, #16]

  (46) 0x406e3c BFM	X14, X4, #0, #30

  (46) 0x406e40 LDR	X12, [X1, #1792]

  (46) 0x406e44 EOR	X30, X7, X14,LSR #1

  (46) 0x406e48 ANDS	XZR, X14, #4096

  (46) 0x406e4c ORR	X16, XZR, X18

  (46) 0x406e50 LDUR	X2, [X1, #488]

  (46) 0x406e54 BFM	X16, X17, #0, #30

  (46) 0x406e58 EOR	X0, X30, X25

  (46) 0x406e5c CSEL	X13, X0, X30, #1

  (46) 0x406e60 STR	X13, [X1, #1784]

  (46) 0x406e64 LDUR	X14, [X1, #496]

  (46) 0x406e68 BFM	X12, X18, #0, #30

  (46) 0x406e6c EOR	X6, X2, X12,LSR #1

  (46) 0x406e70 ANDS	XZR, X12, #4096

  (46) 0x406e74 EOR	X4, X14, X16,LSR #1

  (46) 0x406e78 EOR	X5, X6, X25

  (46) 0x406e7c CSEL	X7, X5, X6, #1

  (46) 0x406e80 STR	X7, [X1, #1792]

  (46) 0x406e84 ANDS	XZR, X16, #4096

  (46) 0x406e88 EOR	X18, X4, X25

  (46) 0x406e8c CSEL	X17, X18, X4, #1

  (46) 0x406e90 STR	X17, [X15, #1816]

  (46) 0x406e94 LDR	X30, [X1, #1808]

  (46) 0x406e98 LDR	X0, [X1, #1816]

  (46) 0x406e9c LDUR	X15, [X1, #504]

  (46) 0x406ea0 BFM	X30, X0, #0, #30

  (46) 0x406ea4 EOR	X13, X15, X30,LSR #1

  (46) 0x406ea8 ANDS	XZR, X30, #4096

  (46) 0x406eac EOR	X2, X13, X25

  (46) 0x406eb0 CSEL	X12, X2, X13, #1

  (46) 0x406eb4 STR	X12, [X24, #1816]

  (46) 0x406eb8 CMP	X8, X1

  (46) 0x406ebc B.NE	406e20

0x406ec0 LDR	X5, [X26]

0x406ec4 MOVZ	X24, #1

0x406ec8 MOVZ	X6, #0

0x406ecc LDR	X7, [X26, #4984]

0x406ed0 LDR	X1, [X26, #3168]

0x406ed4 BFM	X7, X5, #0, #30

0x406ed8 EOR	X16, X1, X7,LSR #1

0x406edc ANDS	XZR, X7, #4096

0x406ee0 EOR	X14, X16, X25

0x406ee4 CSEL	X4, X14, X16, #1

0x406ee8 STR	X4, [X26, #4984]

0x406eec B	406c00

    (49) 0x406ef0 MOVZ	W10, #1

    (49) 0x406ef4 CMP	X24, #624

    (49) 0x406ef8 B.NE	406b30

  (50) 0x406efc SUB	X24, X9, X26

  (50) 0x406f00 ORR	X1, XZR, X26

  (50) 0x406f04 SUB	X5, X24, #8

  (50) 0x406f08 ORR	X18, XZR, X26

  (50) 0x406f0c UBFM	X7, X5, #3, #63

  (50) 0x406f10 ADD	X16, X7, #1

  (50) 0x406f14 ANDS	X14, X16, #4160

  (50) 0x406f18 B.EQ	406fa0

  (50) 0x406f1c CMP	X14, #1

  (50) 0x406f20 B.EQ	406f6c

  (50) 0x406f24 CMP	X14, #2

  (50) 0x406f28 B.EQ	406f4c

  (50) 0x406f2c LDP	X4, X17, [X26]

  (50) 0x406f30 LDR	X15, [X26, #3176]

  (50) 0x406f34 BFM	X4, X17, #0, #30

  (50) 0x406f38 ANDS	XZR, X4, #4096

  (50) 0x406f3c EOR	X30, X15, X4,LSR #1

  (50) 0x406f40 EOR	X0, X30, X25

  (50) 0x406f44 CSEL	X13, X0, X30, #1

  (50) 0x406f48 STR	X13, [X18], #8

  (50) 0x406f4c LDP	X12, X6, [X18]

  (50) 0x406f50 LDR	X2, [X18, #3176]

  (50) 0x406f54 BFM	X12, X6, #0, #30

  (50) 0x406f58 ANDS	XZR, X12, #4096

  (50) 0x406f5c EOR	X24, X2, X12,LSR #1

  (50) 0x406f60 EOR	X5, X24, X25

  (50) 0x406f64 CSEL	X7, X5, X24, #1

  (50) 0x406f68 STR	X7, [X18], #8

  (50) 0x406f6c LDP	X16, X14, [X18]

  (50) 0x406f70 LDR	X4, [X18, #3176]

  (50) 0x406f74 BFM	X16, X14, #0, #30

  (50) 0x406f78 ANDS	XZR, X16, #4096

  (50) 0x406f7c EOR	X17, X4, X16,LSR #1

  (50) 0x406f80 EOR	X15, X17, X25

  (50) 0x406f84 CSEL	X30, X15, X17, #1

  (50) 0x406f88 STR	X30, [X18], #8

  (50) 0x406f8c CMP	X9, X18

  (50) 0x406f90 B.EQ	407038

  (50) 0x406f94 HINT	#0

  (50) 0x406f98 HINT	#0

  (50) 0x406f9c HINT	#0

    (47) 0x406fa0 LDP	X13, X12, [X18]

    (47) 0x406fa4 ORR	X0, XZR, X18

    (47) 0x406fa8 LDR	X6, [X18, #3176]

    (47) 0x406fac BFM	X13, X12, #0, #30

    (47) 0x406fb0 ORR	X7, XZR, X12

    (47) 0x406fb4 ANDS	XZR, X13, #4096

    (47) 0x406fb8 EOR	X2, X6, X13,LSR #1

    (47) 0x406fbc EOR	X24, X2, X25

    (47) 0x406fc0 CSEL	X5, X24, X2, #1

    (47) 0x406fc4 STR	X5, [X0], #8

    (47) 0x406fc8 LDR	X16, [X0, #8]

    (47) 0x406fcc LDR	X14, [X0, #3176]

    (47) 0x406fd0 BFM	X7, X16, #0, #30

    (47) 0x406fd4 ORR	X30, XZR, X16

    (47) 0x406fd8 EOR	X4, X14, X7,LSR #1

    (47) 0x406fdc ANDS	XZR, X7, #4096

    (47) 0x406fe0 EOR	X17, X4, X25

    (47) 0x406fe4 CSEL	X15, X17, X4, #1

    (47) 0x406fe8 STR	X15, [X18, #8]

    (47) 0x406fec LDR	X13, [X0, #16]

    (47) 0x406ff0 LDR	X12, [X0, #3184]

    (47) 0x406ff4 BFM	X30, X13, #0, #30

    (47) 0x406ff8 EOR	X6, X12, X30,LSR #1

    (47) 0x406ffc ANDS	XZR, X30, #4096

    (47) 0x407000 EOR	X2, X6, X25

    (47) 0x407004 CSEL	X24, X2, X6, #1

    (47) 0x407008 STR	X24, [X0, #8]

    (47) 0x40700c LDP	X0, X5, [X18, #24]

    (47) 0x407010 ADD	X18, X18, #32

    (47) 0x407014 LDR	X7, [X18, #3168]

    (47) 0x407018 BFM	X0, X5, #0, #30

    (47) 0x40701c ANDS	XZR, X0, #4096

    (47) 0x407020 EOR	X16, X7, X0,LSR #1

    (47) 0x407024 EOR	X14, X16, X25

    (47) 0x407028 CSEL	X4, X14, X16, #1

    (47) 0x40702c STUR	X4, [X18, #504]

    (47) 0x407030 CMP	X9, X18

    (47) 0x407034 B.NE	406fa0

  (50) 0x407038 SUB	X18, X8, X26

  (50) 0x40703c SUB	X17, X18, #8

  (50) 0x407040 UBFM	X15, X17, #3, #63

  (50) 0x407044 ADD	X30, X15, #1

  (50) 0x407048 ANDS	X13, X30, #4160

  (50) 0x40704c B.EQ	4070e0

  (50) 0x407050 CMP	X13, #1

  (50) 0x407054 B.EQ	4070b0

  (50) 0x407058 CMP	X13, #2

  (50) 0x40705c B.EQ	407088

  (50) 0x407060 LDR	X6, [X26, #1816]

  (50) 0x407064 ADD	X1, X26, #8

  (50) 0x407068 LDR	X2, [X26, #1824]

  (50) 0x40706c LDR	X12, [X26]

  (50) 0x407070 BFM	X6, X2, #0, #30

  (50) 0x407074 EOR	X24, X12, X6,LSR #1

  (50) 0x407078 ANDS	XZR, X6, #4096

  (50) 0x40707c EOR	X0, X24, X25

  (50) 0x407080 CSEL	X5, X0, X24, #1

  (50) 0x407084 STR	X5, [X26, #1816]

  (50) 0x407088 LDR	X16, [X1, #1816]

  (50) 0x40708c ADD	X1, X1, #8

  (50) 0x407090 LDR	X14, [X1, #1816]

  (50) 0x407094 LDUR	X7, [X1, #504]

  (50) 0x407098 BFM	X16, X14, #0, #30

  (50) 0x40709c EOR	X4, X7, X16,LSR #1

  (50) 0x4070a0 ANDS	XZR, X16, #4096

  (50) 0x4070a4 EOR	X18, X4, X25

  (50) 0x4070a8 CSEL	X17, X18, X4, #1

  (50) 0x4070ac STR	X17, [X1, #1808]

  (50) 0x4070b0 LDR	X30, [X1, #1816]

  (50) 0x4070b4 ADD	X1, X1, #8

  (50) 0x4070b8 LDR	X13, [X1, #1816]

  (50) 0x4070bc LDUR	X15, [X1, #504]

  (50) 0x4070c0 BFM	X30, X13, #0, #30

  (50) 0x4070c4 EOR	X12, X15, X30,LSR #1

  (50) 0x4070c8 ANDS	XZR, X30, #4096

  (50) 0x4070cc EOR	X6, X12, X25

  (50) 0x4070d0 CSEL	X2, X6, X12, #1

  (50) 0x4070d4 STR	X2, [X1, #1808]

  (50) 0x4070d8 CMP	X8, X1

  (50) 0x4070dc B.EQ	407180

    (48) 0x4070e0 ADD	X0, X1, #1816

    (48) 0x4070e4 LDR	X14, [X1]

    (48) 0x4070e8 ADD	X7, X1, #16

    (48) 0x4070ec LDP	X5, X16, [X0]

    (48) 0x4070f0 ADD	X24, X1, #24

    (48) 0x4070f4 ADD	X1, X1, #32

    (48) 0x4070f8 LDP	X18, X17, [X0, #16]

    (48) 0x4070fc BFM	X5, X16, #0, #30

    (48) 0x407100 LDR	X12, [X1, #1792]

    (48) 0x407104 EOR	X4, X14, X5,LSR #1

    (48) 0x407108 ANDS	XZR, X5, #4096

    (48) 0x40710c ORR	X0, XZR, X18

    (48) 0x407110 LDUR	X13, [X1, #488]

    (48) 0x407114 BFM	X0, X17, #0, #30

    (48) 0x407118 EOR	X15, X4, X25

    (48) 0x40711c CSEL	X30, X15, X4, #1

    (48) 0x407120 STR	X30, [X1, #1784]

    (48) 0x407124 LDUR	X5, [X1, #496]

    (48) 0x407128 BFM	X12, X18, #0, #30

    (48) 0x40712c EOR	X6, X13, X12,LSR #1

    (48) 0x407130 ANDS	XZR, X12, #4096

    (48) 0x407134 EOR	X16, X5, X0,LSR #1

    (48) 0x407138 EOR	X2, X6, X25

    (48) 0x40713c CSEL	X14, X2, X6, #1

    (48) 0x407140 STR	X14, [X1, #1792]

    (48) 0x407144 ANDS	XZR, X0, #4096

    (48) 0x407148 EOR	X18, X16, X25

    (48) 0x40714c CSEL	X17, X18, X16, #1

    (48) 0x407150 STR	X17, [X7, #1816]

    (48) 0x407154 LDR	X15, [X1, #1808]

    (48) 0x407158 LDR	X4, [X1, #1816]

    (48) 0x40715c LDUR	X7, [X1, #504]

    (48) 0x407160 BFM	X15, X4, #0, #30

    (48) 0x407164 EOR	X30, X7, X15,LSR #1

    (48) 0x407168 ANDS	XZR, X15, #4096

    (48) 0x40716c EOR	X13, X30, X25

    (48) 0x407170 CSEL	X12, X13, X30, #1

    (48) 0x407174 STR	X12, [X24, #1816]

    (48) 0x407178 CMP	X8, X1

    (48) 0x40717c B.NE	4070e0

  (50) 0x407180 LDR	X14, [X26]

  (50) 0x407184 MOVZ	X24, #1

  (50) 0x407188 MOVZ	X6, #0

  (50) 0x40718c LDR	X2, [X26, #4984]

  (50) 0x407190 LDR	X1, [X26, #3168]

  (50) 0x407194 BFM	X2, X14, #0, #30

  (50) 0x407198 EOR	X0, X1, X2,LSR #1

  (50) 0x40719c ANDS	XZR, X2, #4096

  (50) 0x4071a0 EOR	X5, X0, X25

  (50) 0x4071a4 CSEL	X16, X5, X0, #1

  (50) 0x4071a8 STR	X16, [X26, #4984]

  (50) 0x4071ac B	406b38

/usr/include/c++/11/bits/random.tcc: 401 - 3369

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

421:       _M_p = 0;

422:     }

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3358:       _RealType __sum = _RealType(0);

3359:       _RealType __tmp = _RealType(1);

3360:       for (size_t __k = __m; __k != 0; --__k)

3361: 	{

3362: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3363: 	  __tmp *= __r;

3364: 	}

3365:       __ret = __sum / __tmp;

3366:       if (__builtin_expect(__ret >= _RealType(1), 0))

3367: 	{

3368: #if _GLIBCXX_USE_C99_MATH_TR1

3369: 	  __ret = std::nextafter(_RealType(1), _RealType(0));

/usr/include/c++/11/bits/random.h: 1870 - 1870

--------------------------------------------------------------------------------

1870: 	  return (__aurng() * (__p.b() - __p.a())) + __p.a();

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/RandomGenerator.h: 51 - 55

--------------------------------------------------------------------------------

51:     for (int i = 0; i + 1 < n; i += 2)

52:     {

53:       double temp1 = 1.0 - 0.9999999999 * rng(), temp2 = rng();

54:       a[i]     = sqrt(-2.0 * log(temp1)) * cos(6.283185306 * temp2);

55:       a[i + 1] = sqrt(-2.0 * log(temp1)) * sin(6.283185306 * temp2);

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:404	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	9.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	main._omp_fn.1
Source	random.tcc:401-406,random.tcc:409-414,random.tcc:417-422,random.tcc:455-455,random.tcc:462-462,random.tcc:3358-3359,random.tcc:3363-3366,random.tcc:3369-3369,random.h:1870-1870,RandomGenerator.h:51-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	18.25
CQA cycles if fully vectorized	3.34
Front-end cycles	17.25
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	18.25
P2 cycles	18.25
P3 cycles	18.25
P4 cycles	18.25
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	3.50
P13 cycles	3.50
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	140.00
Nb uops	138.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.77
Nb FLOP add-sub	1.00
Nb FLOP mul	4.00
Nb FLOP fma	3.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.90
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.42

Metric	Value
CQA speedup if no scalar integer	9.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	main._omp_fn.1
Source	random.tcc:401-406,random.tcc:409-414,random.tcc:417-422,random.tcc:455-455,random.tcc:462-462,random.tcc:3358-3359,random.tcc:3363-3366,random.tcc:3369-3369,random.h:1870-1870,RandomGenerator.h:51-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	18.25
CQA cycles if fully vectorized	3.34
Front-end cycles	17.25
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	18.25
P2 cycles	18.25
P3 cycles	18.25
P4 cycles	18.25
P5 cycles	6.75
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	3.50
P13 cycles	3.50
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	140.00
Nb uops	138.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.77
Nb FLOP add-sub	1.00
Nb FLOP mul	4.00
Nb FLOP fma	3.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.90
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	random.tcc:401-3369
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/random.tcc:401-422,455-463,3358-3369
/usr/include/c++/11/bits/random.h:1870
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/RandomGenerator.h:51-55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 197 paths individually, rerun with max-paths=197
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 197 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 2.00 cycles (9.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.25 to 3.34 cycles (5.46x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.25 to 1.00 cycles (18.25x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

4: addition or subtraction (3 inside FMA instructions)
7: multiply (3 inside FMA instructions)
2: divide
1: square root

The binary loop is loading 200 bytes. The binary loop is storing 72 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	140
loop length	560
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	18.25	18.25	18.25	18.25	6.75	6.75	6.75	6.75	9.33	9.33	9.33	3.50	3.50
cycles	6.50	6.50	18.25	18.25	18.25	18.25	6.75	6.75	6.75	6.75	9.33	9.33	9.33	3.50	3.50

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	17.25
Overall L1	18.25

Vectorization ratios

all	6%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.25 cycles. At this rate:

11% of peak load performance is reached (10.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.95 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 406bd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
FDIV D16, D6, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X8, #49168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D30, D20, [X27, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X6, #16880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D23, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #1832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X22, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D1, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D31, D20, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCSEL D19, D16, D18, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMADD D21, D31, D19, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMSUB D0, D21, D9, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
CMP X24, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406efc <main._omp_fn.1+0xa14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D24, D23, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMOV D25, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X10, #49168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D26, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCSEL D27, D24, D26, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMADD D14, D31, D27, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
BL 403740 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D28, #-2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D29, D0, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D14, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FSQRT D13, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
BL 403c30 <@plt_start@+0x5b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D30, D31, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X3, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D4, D30, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D31, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STP D4, D0, [X23]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4071b0 <main._omp_fn.1+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X11, #16880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D7, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #1832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D18, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X8, X22, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, #623	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 406c44 <main._omp_fn.1+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406cb4 <main._omp_fn.1+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406c94 <main._omp_fn.1+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X13, [X26, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X30, X0, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X30, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X2, X13, X30,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X12, X2, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X12, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X5, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X6, [X17, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X7, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X7, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X24, X6, X7,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X4, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X16, X4, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [X17, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X14, X18, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X14, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X0, X30, X14,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X13, X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X2, X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406d74 <main._omp_fn.1+0x88c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
SUB X17, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406e20 <main._omp_fn.1+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406dec <main._omp_fn.1+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406dc4 <main._omp_fn.1+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X26, #1824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X6, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X24, X12, X6,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X6, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X15, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X4, X15, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [X26, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X16, X14, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X18, X7, X16,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X16, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X17, X18, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X30, X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [X1, #1808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X13, X2, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X12, X0, X13,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X13, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X6, X12, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X5, X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X1, #1808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406ec0 <main._omp_fn.1+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
LDR X5, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X26, #4984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X26, #3168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X7, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X16, X1, X7,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X7, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X14, X16, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X4, X14, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [X26, #4984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 406c00 <main._omp_fn.1+0x718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	main._omp_fn.1
Source file and lines	random.tcc:401-3369
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/random.tcc:401-422,455-463,3358-3369
/usr/include/c++/11/bits/random.h:1870
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Utilities/RandomGenerator.h:51-55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 197 paths individually, rerun with max-paths=197
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 2.00 cycles (9.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.25 to 1.00 cycles (18.25x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

4: addition or subtraction (3 inside FMA instructions)
7: multiply (3 inside FMA instructions)
2: divide
1: square root

The binary loop is loading 200 bytes. The binary loop is storing 72 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	140
loop length	560
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	18.25	18.25	18.25	18.25	6.75	6.75	6.75	6.75	9.33	9.33	9.33	3.50	3.50
cycles	6.50	6.50	18.25	18.25	18.25	18.25	6.75	6.75	6.75	6.75	9.33	9.33	9.33	3.50	3.50

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	17.25
Overall L1	18.25

Vectorization ratios

all	6%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.25 cycles. At this rate:

11% of peak load performance is reached (10.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.95 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 406bd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
FDIV D16, D6, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X8, #49168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D30, D20, [X27, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X6, #16880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D23, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #1832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X22, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D1, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D31, D20, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCSEL D19, D16, D18, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMADD D21, D31, D19, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMSUB D0, D21, D9, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
CMP X24, #624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406efc <main._omp_fn.1+0xa14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D24, D23, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMOV D25, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X10, #49168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D26, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCSEL D27, D24, D26, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMADD D14, D31, D27, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
BL 403740 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D28, #-2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D29, D0, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D14, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FSQRT D13, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
BL 403c30 <@plt_start@+0x5b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D30, D31, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X3, #22144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #40236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D4, D30, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D31, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STP D4, D0, [X23]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4071b0 <main._omp_fn.1+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X11, #16880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D7, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #1832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D18, X11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X8, X22, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #61382	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, #623	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.HI 406c44 <main._omp_fn.1+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406cb4 <main._omp_fn.1+0x7cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406c94 <main._omp_fn.1+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X13, [X26, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X30, X0, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X30, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X2, X13, X30,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X12, X2, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X12, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X5, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X6, [X17, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X7, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X7, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X24, X6, X7,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X4, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X16, X4, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [X17, #3176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X14, X18, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ANDS XZR, X14, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X0, X30, X14,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X13, X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X2, X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X17], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406d74 <main._omp_fn.1+0x88c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
SUB X17, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406e20 <main._omp_fn.1+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406dec <main._omp_fn.1+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406dc4 <main._omp_fn.1+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X26, #1824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X6, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X24, X12, X6,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X6, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X15, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X4, X15, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [X26, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X16, X14, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X18, X7, X16,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X16, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X17, X18, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X30, X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [X1, #1808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X1, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X13, X2, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X12, X0, X13,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X13, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X6, X12, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X5, X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X1, #1808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 406ec0 <main._omp_fn.1+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
LDR X5, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X26, #4984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X26, #3168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BFM X7, X5, #0, #30	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
EOR X16, X1, X7,LSR #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X7, #4096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
EOR X14, X16, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X4, X14, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [X26, #4984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 406c00 <main._omp_fn.1+0x718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code