OV - exec - Function qmcplusplus::DistanceTableBA<double, 3u, 39>::evaluate(qmcplusplus::ParticleSet&, int)

	Function: qmcplusplus::DistanceTableBA<double, 3u, 39>::evaluate(qmcplusplus::ParticleSet&, int)	Module: exec	Source: stl_vector.h:1046-1046 [...]	Coverage: 0.6%

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 177 - 177

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177:   inline const Type_t& operator[](unsigned int i) const { return X[i]; }

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h: 167 - 217

--------------------------------------------------------------------------------

167:     const T x0 = pos[0];

168:     const T y0 = pos[1];

169:     const T z0 = pos[2];

[...]

185: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

186:     for (int iat = first; iat < last; ++iat)

187:     {

188:       const T flip    = iat < flip_ind ? one : minusone;

189:       const T displ_0 = (px[iat] - x0) * flip;

190:       const T displ_1 = (py[iat] - y0) * flip;

191:       const T displ_2 = (pz[iat] - z0) * flip;

192:

193:       const T ar_0 = -std::floor(displ_0 * g00 + displ_1 * g10 + displ_2 * g20);

194:       const T ar_1 = -std::floor(displ_0 * g01 + displ_1 * g11 + displ_2 * g21);

195:       const T ar_2 = -std::floor(displ_0 * g02 + displ_1 * g12 + displ_2 * g22);

196:

197:       const T delx = displ_0 + ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

198:       const T dely = displ_1 + ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

199:       const T delz = displ_2 + ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

200:

201:       T rmin = delx * delx + dely * dely + delz * delz;

202:       int ic = 0;

203: #pragma unroll(7)

204:       for (int c = 1; c < 8; ++c)

205:       {

206:         const T x  = delx + cellx[c];

207:         const T y  = dely + celly[c];

208:         const T z  = delz + cellz[c];

209:         const T r2 = x * x + y * y + z * z;

210:         ic         = (r2 < rmin) ? c : ic;

211:         rmin       = (r2 < rmin) ? r2 : rmin;

212:       }

213:

214:       temp_r[iat] = std::sqrt(rmin);

215:       dx[iat]     = flip * (delx + cellx[ic]);

216:       dy[iat]     = flip * (dely + celly[ic]);

217:       dz[iat]     = flip * (delz + cellz[ic]);

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

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223:     return X[i];

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 241 - 243

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241:   T* restrict data(size_t i) { return myData + i * nGhosts; }

242:   ///return the const pointer of the i-th components

243:   const T* restrict data(size_t i) const { return myData + i * nGhosts; }

/usr/include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/DistanceTableBA.h: 111 - 114

--------------------------------------------------------------------------------

111:   inline void evaluate(ParticleSet& P, IndexType iat)

112:   {

113:     DTD_BConds<T, D, SC>::computeDistances(P.R[iat], Origin->RSoA, Distances[iat], Displacements[iat], 0, Nsources);

114:   }

0x470540 LDR	X6, [X0, #80]

0x470544 MOVZ	W8, #40

0x470548 MOVZ	W4, #24

0x47054c SBFM	X3, X2, #0, #31

0x470550 LDR	X7, [X0, #24]

0x470554 SMADDL	X12, W2, W4, XZR

0x470558 LDR	X5, [X0, #8]

0x47055c SMADDL	X2, W2, W8, X6

0x470560 LDR	X13, [X0, #64]

0x470564 MADD	X9, X3, X7, XZR

0x470568 LDR	X14, [X2, #8]

0x47056c LDR	X15, [X1, #1512]

0x470570 ADD	X1, X5, #1528

0x470574 ADD	X9, X13, X9,LSL #3

0x470578 LDR	X17, [X5, #1536]

0x47057c UBFM	X16, X14, #61, #60

0x470580 LDR	X13, [X2, #24]

0x470584 ADD	X18, X15, X12

0x470588 LDR	X11, [X1, #24]

0x47058c UBFM	X4, X17, #61, #60

0x470590 LDR	W10, [X0, #196]

0x470594 ADD	X14, X13, X16

0x470598 LDR	D6, [X15, X12]

0x47059c ADD	X8, X14, X16

0x4705a0 ADD	X12, X11, X4

0x4705a4 ADD	X7, X12, X4

0x4705a8 LDP	D7, D16, [X18, #8]

0x4705ac CMP	W10, #0

0x4705b0 B.LE	470824

0x4705b4 STP	X29, X30, [SP, #992]!

0x4705b8 ADD	X29, SP, #0

0x4705bc MOVZ	X3, #0

0x4705c0 ADD	X1, X0, #240

0x4705c4 ADD	X6, X0, #384

0x4705c8 ADD	X5, X0, #448

0x4705cc ADD	X4, X0, #512

0x4705d0 MOVZ	W30, #3

0x4705d4 STR	X19, [SP, #16]

0x4705d8 MOVZ	W18, #4

0x4705dc MOVZ	W17, #5

0x4705e0 MOVZ	W16, #6

0x4705e4 MOVZ	W15, #7

0x4705e8 MOVZ	W19, #2

(1242) 0x4705ec LDR	D1, [X12, X3,LSL #3]

(1242) 0x4705f0 LDR	D2, [X11, X3,LSL #3]

(1242) 0x4705f4 LDP	D17, D5, [X1]

(1242) 0x4705f8 FSUB	D21, D7, S1

(1242) 0x4705fc LDR	D0, [X7, X3,LSL #3]

(1242) 0x470600 FSUB	D22, D6, S2

(1242) 0x470604 LDR	D4, [X1, #32]

(1242) 0x470608 LDR	D3, [X1, #56]

(1242) 0x47060c FMUL	D24, D21, D5

(1242) 0x470610 FSUB	D23, D16, S0

(1242) 0x470614 LDP	D19, D20, [X1, #16]

(1242) 0x470618 LDR	D18, [X1, #96]

(1242) 0x47061c FMUL	D25, D21, D4

(1242) 0x470620 LDP	D1, D2, [X1, #40]

(1242) 0x470624 FMUL	D29, D21, D3

(1242) 0x470628 FMADD	D26, D22, D17, D24

(1242) 0x47062c LDR	D0, [X1, #104]

(1242) 0x470630 FMADD	D27, D22, D20, D25

(1242) 0x470634 LDR	D3, [X1, #64]

(1242) 0x470638 FMADD	D28, D23, D19, D26

(1242) 0x47063c FRINTM	D30, D28

(1242) 0x470640 LDR	D20, [X1, #80]

(1242) 0x470644 FMSUB	D31, D30, D18, D21

(1242) 0x470648 FMADD	D4, D22, D2, D29

(1242) 0x47064c LDR	D21, [X1, #72]

(1242) 0x470650 FMADD	D17, D23, D1, D27

(1242) 0x470654 FRINTM	D5, D17

(1242) 0x470658 LDP	D19, D18, [X1, #112]

(1242) 0x47065c FMSUB	D24, D5, D0, D31

(1242) 0x470660 FMADD	D25, D23, D3, D4

(1242) 0x470664 FRINTM	D26, D25

(1242) 0x470668 LDR	D29, [X1, #88]

(1242) 0x47066c FMSUB	D22, D30, D21, D22

(1242) 0x470670 FMSUB	D23, D30, D18, D23

(1242) 0x470674 LDP	D30, D1, [X1, #128]

(1242) 0x470678 FMSUB	D31, D26, D19, D24

(1242) 0x47067c LDP	D19, D24, [X5, #24]

(1242) 0x470680 FMSUB	D27, D5, D20, D22

(1242) 0x470684 LDP	D3, D20, [X5, #8]

(1242) 0x470688 FMSUB	D21, D5, D30, D23

(1242) 0x47068c LDP	D5, D22, [X4, #8]

(1242) 0x470690 FMSUB	D2, D26, D29, D27

(1242) 0x470694 FMSUB	D0, D26, D1, D21

(1242) 0x470698 LDR	D21, [X4, #24]

(1242) 0x47069c FMUL	D28, D31, D31

(1242) 0x4706a0 FADD	D18, D31, D3

(1242) 0x4706a4 FADD	D23, D31, D24

(1242) 0x4706a8 FADD	D26, D31, D20

(1242) 0x4706ac FADD	D27, D31, D19

(1242) 0x4706b0 LDR	D19, [X6, #24]

(1242) 0x4706b4 FMADD	D17, D2, D2, D28

(1242) 0x4706b8 FMUL	D28, D18, D18

(1242) 0x4706bc FMUL	D1, D23, D23

(1242) 0x4706c0 FMUL	D29, D26, D26

(1242) 0x4706c4 FADD	D18, D2, D19

(1242) 0x4706c8 FADD	D4, D0, D5

(1242) 0x4706cc FMUL	D30, D27, D27

(1242) 0x4706d0 FMADD	D25, D0, D0, D17

(1242) 0x4706d4 LDP	D17, D5, [X6, #8]

(1242) 0x4706d8 FADD	D22, D0, D22

(1242) 0x4706dc FADD	D27, D0, D21

(1242) 0x4706e0 FADD	D3, D2, D17

(1242) 0x4706e4 FADD	D20, D2, D5

(1242) 0x4706e8 FMADD	D24, D3, D3, D28

(1242) 0x4706ec FMADD	D26, D20, D20, D29

(1242) 0x4706f0 FMADD	D28, D18, D18, D30

(1242) 0x4706f4 FMADD	D4, D4, D4, D24

(1242) 0x4706f8 FMINNM	D23, D25, D4

(1242) 0x4706fc FMADD	D29, D22, D22, D26

(1242) 0x470700 FMADD	D21, D27, D27, D28

(1242) 0x470704 FMINNM	D30, D29, D23

(1242) 0x470708 FMINNM	D20, D30, D21

(1242) 0x47070c FCMPE	D25, D4

(1242) 0x470710 LDR	D25, [X6, #32]

(1242) 0x470714 CSINC	W2, WZR, WZR, #13

(1242) 0x470718 FCMPE	D29, D23

(1242) 0x47071c CSEL	W2, W2, W19, #10

(1242) 0x470720 LDR	D5, [X4, #32]

(1242) 0x470724 FCMPE	D30, D21

(1242) 0x470728 CSEL	W2, W2, W30, #9

(1242) 0x47072c LDP	D29, D23, [X5, #40]

(1242) 0x470730 FADD	D17, D2, D25

(1242) 0x470734 LDR	D19, [X4, #48]

(1242) 0x470738 FADD	D3, D0, D5

(1242) 0x47073c LDR	D30, [X5, #56]

(1242) 0x470740 LDR	D22, [X4, #40]

(1242) 0x470744 FADD	D21, D31, D29

(1242) 0x470748 FMADD	D1, D17, D17, D1

(1242) 0x47074c FADD	D27, D0, D19

(1242) 0x470750 LDR	D18, [X4, #56]

(1242) 0x470754 FADD	D17, D31, D23

(1242) 0x470758 LDR	D19, [X6, #56]

(1242) 0x47075c FADD	D5, D31, D30

(1242) 0x470760 FADD	D4, D0, D22

(1242) 0x470764 FMUL	D25, D21, D21

(1242) 0x470768 FMADD	D24, D3, D3, D1

(1242) 0x47076c FMINNM	D26, D20, D24

(1242) 0x470770 FADD	D28, D0, D18

(1242) 0x470774 FMUL	D3, D17, D17

(1242) 0x470778 FADD	D18, D2, D19

(1242) 0x47077c FMUL	D1, D5, D5

(1242) 0x470780 FMADD	D17, D18, D18, D1

(1242) 0x470784 FCMPE	D20, D24

(1242) 0x470788 LDP	D24, D20, [X6, #40]

(1242) 0x47078c CSEL	W2, W2, W18, #9

(1242) 0x470790 FMADD	D28, D28, D28, D17

(1242) 0x470794 FADD	D22, D2, D24

(1242) 0x470798 FADD	D29, D2, D20

(1242) 0x47079c FMADD	D23, D22, D22, D25

(1242) 0x4707a0 FMADD	D30, D29, D29, D3

(1242) 0x4707a4 FMADD	D5, D4, D4, D23

(1242) 0x4707a8 FMADD	D27, D27, D27, D30

(1242) 0x4707ac FMINNM	D21, D26, D5

(1242) 0x4707b0 FMINNM	D4, D21, D27

(1242) 0x4707b4 FMINNM	D25, D28, D4

(1242) 0x4707b8 FSQRT	D3, D25

(1242) 0x4707bc FCMPE	D26, D5

(1242) 0x4707c0 CSEL	W2, W2, W17, #9

(1242) 0x4707c4 FCMPE	D21, D27

(1242) 0x4707c8 CSEL	W2, W2, W16, #9

(1242) 0x4707cc FCMPE	D28, D4

(1242) 0x4707d0 CSEL	W2, W2, W15, #10

(1242) 0x4707d4 ADD	X2, X0, W2,SXTW #3

(1242) 0x4707d8 LDR	D26, [X2, #384]

(1242) 0x4707dc FADD	D2, D2, D26

(1242) 0x4707e0 STR	D3, [X9, X3,LSL #3]

(1242) 0x4707e4 FNEG	D1, D2

(1242) 0x4707e8 STR	D1, [X13, X3,LSL #3]

(1242) 0x4707ec LDR	D24, [X2, #448]

(1242) 0x4707f0 FADD	D31, D31, D24

(1242) 0x4707f4 FNEG	D20, D31

(1242) 0x4707f8 STR	D20, [X14, X3,LSL #3]

(1242) 0x4707fc LDR	D19, [X2, #512]

(1242) 0x470800 FADD	D0, D0, D19

(1242) 0x470804 FNEG	D22, D0

(1242) 0x470808 STR	D22, [X8, X3,LSL #3]

(1242) 0x47080c ADD	X3, X3, #1

(1242) 0x470810 CMP	W10, W3

(1242) 0x470814 B.GT	4705ec

0x470818 LDR	X19, [SP, #16]

0x47081c LDP	X29, X30, [SP], #32

0x470820 RET

0x470824 RET

0x470828 HINT	#0

0x47082c HINT	#0

0x470830 HINT	#0

0x470834 HINT	#0

0x470838 HINT	#0

0x47083c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::ParticleSet::setA[...]	stl_vector.h:919	exec
○	main._omp_fn.1	refwrap.h:337	exec
○	GOMP_parallel		libomp.so
○	main	miniqmc.cpp:402	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	stl_vector.h:1046-1046
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:167-169,185-217
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:241-243
/usr/include/c++/11/bits/stl_vector.h:1046
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/DistanceTableBA.h:111-114

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 0.67 cycles (10.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.25 to 1.12 cycles (6.44x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00
cycles	1.50	1.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.88
Overall L1	7.25

Vectorization ratios

all	6%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

17% of peak load performance is reached (17.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 470540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X6, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SMADDL X12, W2, W4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SMADDL X2, W2, W8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X13, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X3, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X1, #1512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X5, #1528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X13, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X5, #1536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X0, #196]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X8, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X12, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D7, D16, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 470824 <_ZN11qmcplusplus15DistanceTableBAIdLj3ELi39EE8evaluateERNS_11ParticleSetEi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X29, X30, [SP, #992]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X0, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X0, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	stl_vector.h:1046-1046
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:167-169,185-217
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:241-243
/usr/include/c++/11/bits/stl_vector.h:1046
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/DistanceTableBA.h:111-114

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 0.67 cycles (10.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00
cycles	1.50	1.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	1.00	1.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.88
Overall L1	7.25

Vectorization ratios

all	6%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

17% of peak load performance is reached (17.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 470540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X6, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SMADDL X12, W2, W4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SMADDL X2, W2, W8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X13, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X3, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X1, #1512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X5, #1528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X13, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X5, #1536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X0, #196]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X8, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X12, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D7, D16, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 470824 <_ZN11qmcplusplus15DistanceTableBAIdLj3ELi39EE8evaluateERNS_11ParticleSetEi+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X29, X30, [SP, #992]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X0, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X0, #512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::DistanceTableBA::evaluate(qmcplusplus::ParticleSet&, int)–	0.6	0
○Loop 1242 - ParticleBConds.h:189-217 - exec	0.6	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code