OV - exec - Loop 946

  (948) 0x432600 LDR	X4, [SP, #304]

  (948) 0x432604 LDP	X13, X18, [SP, #352]

  (948) 0x432608 LDP	X16, X1, [SP, #336]

  (948) 0x43260c LDP	X26, X30, [SP, #320]

    (945) 0x432610 LDR	X9, [SP, #312]

    (945) 0x432614 ADD	X18, X18, #1

    (945) 0x432618 CMP	X18, #4

    (945) 0x43261c ADD	X13, X13, X9

    (945) 0x432620 ADD	X1, X1, X9

    (945) 0x432624 ADD	X16, X16, X9

    (945) 0x432628 ADD	X30, X30, X9

    (945) 0x43262c ADD	X26, X26, X9

    (945) 0x432630 B.EQ	43298c

    (945) 0x432634 CMP	W4, #1

    (945) 0x432638 B.LT	432610

  (948) 0x43263c SUB	X9, X29, #240

  (948) 0x432640 ORR	X7, XZR, XZR

  (948) 0x432644 ORR	X15, XZR, X1

  (948) 0x432648 STP	X26, X30, [SP, #320]

  (948) 0x43264c STP	X13, X18, [SP, #352]

  (948) 0x432650 STP	X16, X1, [SP, #336]

  (948) 0x432654 ORR	X14, XZR, X13

  (948) 0x432658 LDR	D0, [X9, X18,LSL #3]

  (948) 0x43265c SUB	X9, X29, #176

  (948) 0x432660 LDR	D2, [X9, X18,LSL #3]

  (948) 0x432664 SUB	X9, X29, #112

  (948) 0x432668 LDR	D26, [X9, X18,LSL #3]

  (948) 0x43266c STP	D2, D0, [SP, #384]

  (948) 0x432670 STR	D26, [SP, #376]

  (948) 0x432674 B	4326a0

  (948) 0x432680 ADD	X7, X7, #1

  (948) 0x432684 ADD	X14, X14, X12

  (948) 0x432688 ADD	X15, X15, X12

  (948) 0x43268c CMP	X7, #4

  (948) 0x432690 ADD	X16, X16, X12

  (948) 0x432694 ADD	X30, X30, X12

  (948) 0x432698 ADD	X26, X26, X12

  (948) 0x43269c B.EQ	432600

  (948) 0x4326a0 SUB	X9, X29, #144

  (948) 0x4326a4 LDR	D16, [X6, X7,LSL #3]

  (948) 0x4326a8 CMP	X8, #4

  (948) 0x4326ac LDR	D5, [X9, X7,LSL #3]

  (948) 0x4326b0 SUB	X9, X29, #208

  (948) 0x4326b4 LDR	D7, [X9, X7,LSL #3]

  (948) 0x4326b8 FMUL	D16, D16, D26

  (948) 0x4326bc FMUL	D3, D5, D0

  (948) 0x4326c0 FMUL	D4, D2, D5

  (948) 0x4326c4 FMUL	D5, D26, D5

  (948) 0x4326c8 FMUL	D6, D7, D2

  (948) 0x4326cc FMUL	D7, D7, D26

  (948) 0x4326d0 B.CS	4326e0

  (948) 0x4326d4 ORR	X10, XZR, XZR

  (948) 0x4326d8 B	432878

0x4326e0 ORR	X2, XZR, XZR

0x4326e4 ORR	X13, XZR, X3

0x4326e8 ORR	V0.16B, V25.16B, V25.16B

  (944) 0x4326ec ADD	X9, X14, X2

  (944) 0x4326f0 ORR	V2.16B, V1.16B, V1.16B

  (944) 0x4326f4 ORR	V1.16B, V8.16B, V8.16B

  (944) 0x4326f8 ADD	X10, X19, X2

  (944) 0x4326fc SUBS	X13, X13, #4

  (944) 0x432700 LDP	Q25, Q28, [X9]

  (944) 0x432704 ADD	X9, X15, X2

  (944) 0x432708 ORR	V8.16B, V30.16B, V30.16B

  (944) 0x43270c LDP	Q24, Q27, [X9]

  (944) 0x432710 ADD	X9, X16, X2

  (944) 0x432714 LDP	Q26, Q23, [X9]

  (944) 0x432718 ADD	X9, X30, X2

  (944) 0x43271c FMUL	V17.2D, V28.2D, V11.D[0]

  (944) 0x432720 FMUL	V19.2D, V28.2D, V31.D[0]

  (944) 0x432724 FMUL	V28.2D, V28.2D, V0.D[0]

  (944) 0x432728 LDP	Q22, Q21, [X9]

  (944) 0x43272c FMUL	V18.2D, V25.2D, V11.D[0]

  (944) 0x432730 FMUL	V20.2D, V25.2D, V31.D[0]

  (944) 0x432734 ADD	X9, X20, X2

  (944) 0x432738 FMUL	V25.2D, V25.2D, V0.D[0]

  (944) 0x43273c FMLA	V17.2D, V27.2D, V13.D[0]

  (944) 0x432740 FMUL	V29.2D, V24.2D, V30.D[0]

  (944) 0x432744 FMUL	V30.2D, V27.2D, V30.D[0]

  (944) 0x432748 FMLA	V19.2D, V23.2D, V9.D[0]

  (944) 0x43274c FMLA	V18.2D, V24.2D, V13.D[0]

  (944) 0x432750 FMLA	V20.2D, V26.2D, V9.D[0]

  (944) 0x432754 FMLA	V30.2D, V21.2D, V12.D[0]

  (944) 0x432758 FMLA	V17.2D, V23.2D, V14.D[0]

  (944) 0x43275c FMLA	V29.2D, V22.2D, V12.D[0]

  (944) 0x432760 FMLA	V18.2D, V26.2D, V14.D[0]

  (944) 0x432764 FMLA	V19.2D, V30.2D, V10.D[0]

  (944) 0x432768 FMLA	V17.2D, V21.2D, V15.D[0]

  (944) 0x43276c FMLA	V20.2D, V29.2D, V10.D[0]

  (944) 0x432770 LDP	Q29, Q30, [X9]

  (944) 0x432774 FMLA	V18.2D, V22.2D, V15.D[0]

  (944) 0x432778 FMLA	V30.2D, V17.2D, V3.D[0]

  (944) 0x43277c FMLA	V29.2D, V18.2D, V3.D[0]

  (944) 0x432780 STP	Q29, Q30, [X9]

  (944) 0x432784 ADD	X9, X9, X27

  (944) 0x432788 LDP	Q29, Q30, [X9]

  (944) 0x43278c FMLA	V30.2D, V17.2D, V6.D[0]

  (944) 0x432790 FMLA	V29.2D, V18.2D, V6.D[0]

  (944) 0x432794 STP	Q29, Q30, [X9]

  (944) 0x432798 ADD	X9, X9, X27

  (944) 0x43279c LDP	Q29, Q30, [X9]

  (944) 0x4327a0 FMLA	V30.2D, V19.2D, V4.D[0]

  (944) 0x4327a4 FMLA	V29.2D, V20.2D, V4.D[0]

  (944) 0x4327a8 STP	Q29, Q30, [X9]

  (944) 0x4327ac ORR	V30.16B, V8.16B, V8.16B

  (944) 0x4327b0 ORR	V8.16B, V1.16B, V1.16B

  (944) 0x4327b4 ADD	X9, X9, X27

  (944) 0x4327b8 ORR	V1.16B, V2.16B, V2.16B

  (944) 0x4327bc FMLA	V28.2D, V27.2D, V8.D[0]

  (944) 0x4327c0 LDP	Q27, Q29, [X9]

  (944) 0x4327c4 FMLA	V25.2D, V24.2D, V8.D[0]

  (944) 0x4327c8 FMLA	V29.2D, V17.2D, V16.D[0]

  (944) 0x4327cc FMLA	V25.2D, V26.2D, V2.D[0]

  (944) 0x4327d0 FMLA	V28.2D, V23.2D, V2.D[0]

  (944) 0x4327d4 FMLA	V27.2D, V18.2D, V16.D[0]

  (944) 0x4327d8 FMLA	V28.2D, V21.2D, V10.D[0]

  (944) 0x4327dc FMLA	V25.2D, V22.2D, V10.D[0]

  (944) 0x4327e0 STP	Q27, Q29, [X9]

  (944) 0x4327e4 ADD	X9, X9, X27

  (944) 0x4327e8 LDP	Q29, Q27, [X10]

  (944) 0x4327ec LDP	Q24, Q26, [X9]

  (944) 0x4327f0 FMLA	V27.2D, V17.2D, V4.D[0]

  (944) 0x4327f4 FMLA	V29.2D, V18.2D, V4.D[0]

  (944) 0x4327f8 FMLA	V26.2D, V19.2D, V7.D[0]

  (944) 0x4327fc FMLA	V24.2D, V20.2D, V7.D[0]

  (944) 0x432800 STP	Q29, Q27, [X10]

  (944) 0x432804 ADD	X10, X23, X2

  (944) 0x432808 STP	Q24, Q26, [X9]

  (944) 0x43280c LDP	Q23, Q24, [X10]

  (944) 0x432810 ADD	X9, X9, X27

  (944) 0x432814 FMLA	V24.2D, V17.2D, V7.D[0]

  (944) 0x432818 FMLA	V23.2D, V18.2D, V7.D[0]

  (944) 0x43281c STP	Q23, Q24, [X10]

  (944) 0x432820 ADD	X10, X22, X2

  (944) 0x432824 LDP	Q22, Q21, [X10]

  (944) 0x432828 FMLA	V21.2D, V17.2D, V5.D[0]

  (944) 0x43282c FMLA	V22.2D, V18.2D, V5.D[0]

  (944) 0x432830 STP	Q22, Q21, [X10]

  (944) 0x432834 ADD	X10, X24, X2

  (944) 0x432838 ADD	X2, X2, #32

  (944) 0x43283c LDP	Q17, Q18, [X10]

  (944) 0x432840 FMLA	V18.2D, V19.2D, V5.D[0]

  (944) 0x432844 FMLA	V17.2D, V20.2D, V5.D[0]

  (944) 0x432848 STP	Q17, Q18, [X10]

  (944) 0x43284c LDP	Q17, Q18, [X9]

  (944) 0x432850 FMLA	V18.2D, V28.2D, V5.D[0]

  (944) 0x432854 FMLA	V17.2D, V25.2D, V5.D[0]

  (944) 0x432858 STP	Q17, Q18, [X9]

  (944) 0x43285c B.NE	4326ec

0x432860 ORR	V25.16B, V0.16B, V0.16B

0x432864 LDP	D2, D0, [SP, #384]

0x432868 LDR	D26, [SP, #376]

0x43286c LDR	X9, [SP, #368]

0x432870 ORR	X10, XZR, X3

0x432874 CBZ	X9, 432680

  (948) 0x432878 UBFM	X9, X10, #61, #60

  (948) 0x43287c ORR	X13, XZR, XZR

  (948) 0x432880 SUB	X10, X8, X10

  (948) 0x432884 ADD	X2, X26, X9

  (948) 0x432888 ADD	X21, X15, X9

  (948) 0x43288c ADD	X11, X16, X9

  (948) 0x432890 ADD	X1, X30, X9

  (948) 0x432894 ADD	X25, X20, X9

  (948) 0x432898 ADD	X28, X19, X9

  (948) 0x43289c ADD	X17, X23, X9

  (948) 0x4328a0 ADD	X18, X0, X9

  (948) 0x4328a4 ADD	X9, X22, X9

    (947) 0x4328a8 UBFM	X4, X13, #61, #60

    (947) 0x4328ac ADD	X13, X13, #1

    (947) 0x4328b0 LDR	D17, [X2, X4]

    (947) 0x4328b4 LDR	D18, [X21, X4]

    (947) 0x4328b8 LDR	D19, [X11, X4]

    (947) 0x4328bc LDR	D20, [X1, X4]

    (947) 0x4328c0 ADD	X5, X25, X4

    (947) 0x4328c4 CMP	X10, X13

    (947) 0x4328c8 FMUL	D21, D17, D11

    (947) 0x4328cc FMUL	D22, D17, D31

    (947) 0x4328d0 FMUL	D23, D18, D30

    (947) 0x4328d4 FMUL	D17, D17, D25

    (947) 0x4328d8 FMADD	D21, D18, D13, D21

    (947) 0x4328dc FMADD	D23, D12, D20, D23

    (947) 0x4328e0 FMADD	D22, D19, D9, D22

    (947) 0x4328e4 FMADD	D17, D18, D8, D17

    (947) 0x4328e8 FMADD	D21, D19, D14, D21

    (947) 0x4328ec FMADD	D22, D23, D10, D22

    (947) 0x4328f0 LDR	D23, [X5]

    (947) 0x4328f4 FMADD	D17, D19, D1, D17

    (947) 0x4328f8 LDR	D19, [X28, X4]

    (947) 0x4328fc FMADD	D21, D15, D20, D21

    (947) 0x432900 FMADD	D17, D20, D10, D17

    (947) 0x432904 FMADD	D23, D3, D21, D23

    (947) 0x432908 FMADD	D19, D21, D4, D19

    (947) 0x43290c STR	D23, [X5]

    (947) 0x432910 ADD	X5, X5, X27

    (947) 0x432914 STR	D19, [X28, X4]

    (947) 0x432918 LDR	D19, [X17, X4]

    (947) 0x43291c LDR	D23, [X5]

    (947) 0x432920 FMADD	D19, D21, D7, D19

    (947) 0x432924 FMADD	D23, D6, D21, D23

    (947) 0x432928 STR	D19, [X17, X4]

    (947) 0x43292c STR	D23, [X5]

    (947) 0x432930 ADD	X5, X5, X27

    (947) 0x432934 LDR	D19, [X18, X4]

    (947) 0x432938 LDR	D18, [X5]

    (947) 0x43293c FMADD	D19, D22, D5, D19

    (947) 0x432940 FMADD	D18, D22, D4, D18

    (947) 0x432944 STR	D19, [X18, X4]

    (947) 0x432948 STR	D18, [X5]

    (947) 0x43294c ADD	X5, X5, X27

    (947) 0x432950 LDR	D18, [X5]

    (947) 0x432954 FMADD	D18, D16, D21, D18

    (947) 0x432958 STR	D18, [X5]

    (947) 0x43295c ADD	X5, X5, X27

    (947) 0x432960 LDR	D18, [X5]

    (947) 0x432964 FMADD	D18, D22, D7, D18

    (947) 0x432968 STR	D18, [X5]

    (947) 0x43296c LDR	D18, [X5, X27]

    (947) 0x432970 FMADD	D17, D17, D5, D18

    (947) 0x432974 LDR	D18, [X9, X4]

    (947) 0x432978 STR	D17, [X5, X27]

    (947) 0x43297c FMADD	D18, D21, D5, D18

    (947) 0x432980 STR	D18, [X9, X4]

    (947) 0x432984 B.NE	4328a8

  (948) 0x432988 B	432680

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 233 - 270

--------------------------------------------------------------------------------

233:   for (int i = 0; i < 4; i++)

234:     for (int j = 0; j < 4; j++)

[...]

241:       const T pre20 = d2a[i] * b[j];

242:       const T pre10 = da[i] * b[j];

243:       const T pre00 = a[i] * b[j];

244:       const T pre11 = da[i] * db[j];

245:       const T pre01 = a[i] * db[j];

246:       const T pre02 = a[i] * d2b[j];

247:

248:       const int iSplitPoint = num_splines;

249: #pragma omp simd aligned(coefs, coefszs, coefs2zs, coefs3zs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_)

250:       for (int n = 0; n < iSplitPoint; n++)

251:       {

252:         T coefsv    = coefs[n];

253:         T coefsvzs  = coefszs[n];

254:         T coefsv2zs = coefs2zs[n];

255:         T coefsv3zs = coefs3zs[n];

256:

257:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

258:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

259:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

260:

261:         hxx[n] += pre20 * sum0;

262:         hxy[n] += pre11 * sum0;

263:         hxz[n] += pre10 * sum1;

264:         hyy[n] += pre02 * sum0;

265:         hyz[n] += pre01 * sum1;

266:         hzz[n] += pre00 * sum2;

267:         gx[n] += pre10 * sum0;

268:         gy[n] += pre01 * sum0;

269:         gz[n] += pre00 * sum1;

270:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:249-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	0.67
CQA cycles if FP arith vectorized	1.13
CQA cycles if fully vectorized	0.38
Front-end cycles	1.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.44
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	35.71
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.00

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:249-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	0.67
CQA cycles if FP arith vectorized	1.13
CQA cycles if fully vectorized	0.38
Front-end cycles	1.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.44
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	35.71
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:233-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:233-234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:249-250.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.13 to 0.67 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.37 cycles (3.00x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.50	0.50	0.50	0.50	1.00	1.00	1.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.50	0.50	0.50	0.50	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.13
Overall L1	1.13

Vectorization ratios

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles. At this rate:

29% of peak load performance is reached (28.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4326e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V0.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V25.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D2, D0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D26, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X9, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X10, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBZ X9, 432680 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:233-270
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:233-234,241-270.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:249-250.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.13 to 0.67 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.37 cycles (3.00x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.50	0.50	0.50	0.50	1.00	1.00	1.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.50	0.50	0.50	0.50	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.13
Overall L1	1.13

Vectorization ratios

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles. At this rate:

29% of peak load performance is reached (28.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4326e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR V0.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ORR V25.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D2, D0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D26, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X9, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X10, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBZ X9, 432680 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code