OV - exec - Loop 934

  (936) 0x431900 ADD	X8, X8, #1

  (936) 0x431904 ADD	X10, X10, X11

  (936) 0x431908 ADD	X12, X12, X11

  (936) 0x43190c CMP	X8, #4

  (936) 0x431910 ADD	X13, X13, X11

  (936) 0x431914 ADD	X14, X14, X11

  (936) 0x431918 ADD	X15, X15, X11

  (936) 0x43191c ADD	X16, X16, X11

  (936) 0x431920 ADD	X17, X17, X11

  (936) 0x431924 ADD	X18, X18, X11

  (936) 0x431928 ADD	X0, X0, X11

  (936) 0x43192c ADD	X1, X1, X11

  (936) 0x431930 ADD	X2, X2, X11

  (936) 0x431934 ADD	X3, X3, X11

  (936) 0x431938 ADD	X4, X4, X11

  (936) 0x43193c ADD	X5, X5, X11

  (936) 0x431940 ADD	X6, X6, X11

  (936) 0x431944 ADD	X7, X7, X11

  (936) 0x431948 ADD	X21, X21, X11

  (936) 0x43194c B.EQ	431d1c

  (936) 0x431950 LDR	D16, [X22, X8,LSL #3]

  (936) 0x431954 CMP	X19, #4

  (936) 0x431958 FMUL	D17, D0, D16

  (936) 0x43195c B.CS	431968

  (936) 0x431960 ORR	X27, XZR, XZR

  (936) 0x431964 B	4319ec

  (936) 0x431968 ORR	X23, XZR, XZR

  (936) 0x43196c ORR	X24, XZR, X9

  (936) 0x431970 HINT	#0

  (936) 0x431974 HINT	#0

  (936) 0x431978 HINT	#0

  (936) 0x43197c HINT	#0

    (931) 0x431980 ADD	X25, X10, X23

    (931) 0x431984 SUBS	X24, X24, #4

    (931) 0x431988 LDP	Q19, Q18, [X25]

    (931) 0x43198c ADD	X25, X12, X23

    (931) 0x431990 LDP	Q21, Q20, [X25]

    (931) 0x431994 ADD	X25, X13, X23

    (931) 0x431998 FMUL	V18.2D, V18.2D, V4.D[0]

    (931) 0x43199c FMUL	V19.2D, V19.2D, V4.D[0]

    (931) 0x4319a0 FMLA	V18.2D, V20.2D, V5.D[0]

    (931) 0x4319a4 FMLA	V19.2D, V21.2D, V5.D[0]

    (931) 0x4319a8 LDP	Q20, Q21, [X25]

    (931) 0x4319ac ADD	X25, X14, X23

    (931) 0x4319b0 FMLA	V18.2D, V21.2D, V6.D[0]

    (931) 0x4319b4 FMLA	V19.2D, V20.2D, V6.D[0]

    (931) 0x4319b8 LDP	Q21, Q20, [X25]

    (931) 0x4319bc ADD	X25, X20, X23

    (931) 0x4319c0 ADD	X23, X23, #32

    (931) 0x4319c4 FMLA	V18.2D, V20.2D, V7.D[0]

    (931) 0x4319c8 FMLA	V19.2D, V21.2D, V7.D[0]

    (931) 0x4319cc LDP	Q20, Q21, [X25]

    (931) 0x4319d0 FMLA	V21.2D, V18.2D, V17.D[0]

    (931) 0x4319d4 FMLA	V20.2D, V19.2D, V17.D[0]

    (931) 0x4319d8 STP	Q20, Q21, [X25]

    (931) 0x4319dc B.NE	431980

  (936) 0x4319e0 ORR	X27, XZR, X9

  (936) 0x4319e4 CMP	X9, X19

  (936) 0x4319e8 B.EQ	431a44

  (936) 0x4319ec UBFM	X30, X27, #61, #60

  (936) 0x4319f0 ORR	X23, XZR, XZR

  (936) 0x4319f4 SUB	X27, X19, X27

  (936) 0x4319f8 ADD	X24, X14, X30

  (936) 0x4319fc ADD	X25, X13, X30

  (936) 0x431a00 ADD	X26, X12, X30

  (936) 0x431a04 ADD	X28, X20, X30

  (936) 0x431a08 ADD	X30, X15, X30

    (939) 0x431a0c LDR	D18, [X30, X23,LSL #3]

    (939) 0x431a10 LDR	D19, [X26, X23,LSL #3]

    (939) 0x431a14 FMUL	D18, D18, D4

    (939) 0x431a18 FMADD	D18, D19, D5, D18

    (939) 0x431a1c LDR	D19, [X25, X23,LSL #3]

    (939) 0x431a20 FMADD	D18, D19, D6, D18

    (939) 0x431a24 LDR	D19, [X24, X23,LSL #3]

    (939) 0x431a28 FMADD	D18, D7, D19, D18

    (939) 0x431a2c LDR	D19, [X28, X23,LSL #3]

    (939) 0x431a30 FMADD	D18, D17, D18, D19

    (939) 0x431a34 STR	D18, [X28, X23,LSL #3]

    (939) 0x431a38 ADD	X23, X23, #1

    (939) 0x431a3c CMP	X27, X23

    (939) 0x431a40 B.NE	431a0c

  (936) 0x431a44 FMUL	D17, D1, D16

  (936) 0x431a48 CMP	X19, #4

  (936) 0x431a4c B.CS	431a60

  (936) 0x431a50 ORR	X25, XZR, XZR

  (936) 0x431a54 B	431ad4

  (936) 0x431a60 ORR	X23, XZR, XZR

  (936) 0x431a64 ORR	X24, XZR, X9

    (932) 0x431a68 ADD	X25, X16, X23

    (932) 0x431a6c SUBS	X24, X24, #4

    (932) 0x431a70 LDP	Q19, Q18, [X25]

    (932) 0x431a74 ADD	X25, X17, X23

    (932) 0x431a78 LDP	Q21, Q20, [X25]

    (932) 0x431a7c ADD	X25, X18, X23

    (932) 0x431a80 FMUL	V18.2D, V18.2D, V4.D[0]

    (932) 0x431a84 FMUL	V19.2D, V19.2D, V4.D[0]

    (932) 0x431a88 FMLA	V18.2D, V20.2D, V5.D[0]

    (932) 0x431a8c FMLA	V19.2D, V21.2D, V5.D[0]

    (932) 0x431a90 LDP	Q20, Q21, [X25]

    (932) 0x431a94 ADD	X25, X0, X23

    (932) 0x431a98 FMLA	V18.2D, V21.2D, V6.D[0]

    (932) 0x431a9c FMLA	V19.2D, V20.2D, V6.D[0]

    (932) 0x431aa0 LDP	Q21, Q20, [X25]

    (932) 0x431aa4 ADD	X25, X20, X23

    (932) 0x431aa8 ADD	X23, X23, #32

    (932) 0x431aac FMLA	V18.2D, V20.2D, V7.D[0]

    (932) 0x431ab0 FMLA	V19.2D, V21.2D, V7.D[0]

    (932) 0x431ab4 LDP	Q20, Q21, [X25]

    (932) 0x431ab8 FMLA	V21.2D, V18.2D, V17.D[0]

    (932) 0x431abc FMLA	V20.2D, V19.2D, V17.D[0]

    (932) 0x431ac0 STP	Q20, Q21, [X25]

    (932) 0x431ac4 B.NE	431a68

  (936) 0x431ac8 ORR	X25, XZR, X9

  (936) 0x431acc CMP	X9, X19

  (936) 0x431ad0 B.EQ	431b38

  (936) 0x431ad4 UBFM	X30, X25, #61, #60

  (936) 0x431ad8 ORR	X23, XZR, XZR

  (936) 0x431adc SUB	X24, X19, X25

  (936) 0x431ae0 ADD	X25, X20, X30

  (936) 0x431ae4 ADD	X26, X0, X30

  (936) 0x431ae8 ADD	X27, X18, X30

  (936) 0x431aec ADD	X28, X17, X30

  (936) 0x431af0 ADD	X30, X16, X30

  (936) 0x431af4 HINT	#0

  (936) 0x431af8 HINT	#0

  (936) 0x431afc HINT	#0

    (938) 0x431b00 LDR	D18, [X30, X23,LSL #3]

    (938) 0x431b04 LDR	D19, [X28, X23,LSL #3]

    (938) 0x431b08 FMUL	D18, D18, D4

    (938) 0x431b0c FMADD	D18, D19, D5, D18

    (938) 0x431b10 LDR	D19, [X27, X23,LSL #3]

    (938) 0x431b14 FMADD	D18, D19, D6, D18

    (938) 0x431b18 LDR	D19, [X26, X23,LSL #3]

    (938) 0x431b1c FMADD	D18, D7, D19, D18

    (938) 0x431b20 LDR	D19, [X25, X23,LSL #3]

    (938) 0x431b24 FMADD	D18, D17, D18, D19

    (938) 0x431b28 STR	D18, [X25, X23,LSL #3]

    (938) 0x431b2c ADD	X23, X23, #1

    (938) 0x431b30 CMP	X24, X23

    (938) 0x431b34 B.NE	431b00

  (936) 0x431b38 FMUL	D17, D2, D16

  (936) 0x431b3c CMP	X19, #4

  (936) 0x431b40 B.CS	431b4c

  (936) 0x431b44 ORR	X25, XZR, XZR

  (936) 0x431b48 B	431bcc

  (936) 0x431b4c ORR	X23, XZR, XZR

  (936) 0x431b50 ORR	X24, XZR, X9

  (936) 0x431b54 HINT	#0

  (936) 0x431b58 HINT	#0

  (936) 0x431b5c HINT	#0

    (933) 0x431b60 ADD	X25, X1, X23

    (933) 0x431b64 SUBS	X24, X24, #4

    (933) 0x431b68 LDP	Q19, Q18, [X25]

    (933) 0x431b6c ADD	X25, X2, X23

    (933) 0x431b70 LDP	Q21, Q20, [X25]

    (933) 0x431b74 ADD	X25, X3, X23

    (933) 0x431b78 FMUL	V18.2D, V18.2D, V4.D[0]

    (933) 0x431b7c FMUL	V19.2D, V19.2D, V4.D[0]

    (933) 0x431b80 FMLA	V18.2D, V20.2D, V5.D[0]

    (933) 0x431b84 FMLA	V19.2D, V21.2D, V5.D[0]

    (933) 0x431b88 LDP	Q20, Q21, [X25]

    (933) 0x431b8c ADD	X25, X4, X23

    (933) 0x431b90 FMLA	V18.2D, V21.2D, V6.D[0]

    (933) 0x431b94 FMLA	V19.2D, V20.2D, V6.D[0]

    (933) 0x431b98 LDP	Q21, Q20, [X25]

    (933) 0x431b9c ADD	X25, X20, X23

    (933) 0x431ba0 ADD	X23, X23, #32

    (933) 0x431ba4 FMLA	V18.2D, V20.2D, V7.D[0]

    (933) 0x431ba8 FMLA	V19.2D, V21.2D, V7.D[0]

    (933) 0x431bac LDP	Q20, Q21, [X25]

    (933) 0x431bb0 FMLA	V21.2D, V18.2D, V17.D[0]

    (933) 0x431bb4 FMLA	V20.2D, V19.2D, V17.D[0]

    (933) 0x431bb8 STP	Q20, Q21, [X25]

    (933) 0x431bbc B.NE	431b60

  (936) 0x431bc0 ORR	X25, XZR, X9

  (936) 0x431bc4 CMP	X9, X19

  (936) 0x431bc8 B.EQ	431c24

  (936) 0x431bcc UBFM	X30, X25, #61, #60

  (936) 0x431bd0 ORR	X23, XZR, XZR

  (936) 0x431bd4 SUB	X24, X19, X25

  (936) 0x431bd8 ADD	X25, X20, X30

  (936) 0x431bdc ADD	X26, X4, X30

  (936) 0x431be0 ADD	X27, X3, X30

  (936) 0x431be4 ADD	X28, X2, X30

  (936) 0x431be8 ADD	X30, X1, X30

    (937) 0x431bec LDR	D18, [X30, X23,LSL #3]

    (937) 0x431bf0 LDR	D19, [X28, X23,LSL #3]

    (937) 0x431bf4 FMUL	D18, D18, D4

    (937) 0x431bf8 FMADD	D18, D19, D5, D18

    (937) 0x431bfc LDR	D19, [X27, X23,LSL #3]

    (937) 0x431c00 FMADD	D18, D19, D6, D18

    (937) 0x431c04 LDR	D19, [X26, X23,LSL #3]

    (937) 0x431c08 FMADD	D18, D7, D19, D18

    (937) 0x431c0c LDR	D19, [X25, X23,LSL #3]

    (937) 0x431c10 FMADD	D18, D17, D18, D19

    (937) 0x431c14 STR	D18, [X25, X23,LSL #3]

    (937) 0x431c18 ADD	X23, X23, #1

    (937) 0x431c1c CMP	X24, X23

    (937) 0x431c20 B.NE	431bec

  (936) 0x431c24 FMUL	D16, D3, D16

  (936) 0x431c28 CMP	X19, #4

  (936) 0x431c2c B.CS	431c40

  (936) 0x431c30 ORR	X25, XZR, XZR

  (936) 0x431c34 B	431cb4

0x431c40 ORR	X23, XZR, XZR

0x431c44 ORR	X24, XZR, X9

  (930) 0x431c48 ADD	X25, X5, X23

  (930) 0x431c4c SUBS	X24, X24, #4

  (930) 0x431c50 LDP	Q18, Q17, [X25]

  (930) 0x431c54 ADD	X25, X6, X23

  (930) 0x431c58 LDP	Q20, Q19, [X25]

  (930) 0x431c5c ADD	X25, X7, X23

  (930) 0x431c60 FMUL	V17.2D, V17.2D, V4.D[0]

  (930) 0x431c64 FMUL	V18.2D, V18.2D, V4.D[0]

  (930) 0x431c68 FMLA	V17.2D, V19.2D, V5.D[0]

  (930) 0x431c6c FMLA	V18.2D, V20.2D, V5.D[0]

  (930) 0x431c70 LDP	Q19, Q20, [X25]

  (930) 0x431c74 ADD	X25, X21, X23

  (930) 0x431c78 FMLA	V17.2D, V20.2D, V6.D[0]

  (930) 0x431c7c FMLA	V18.2D, V19.2D, V6.D[0]

  (930) 0x431c80 LDP	Q20, Q19, [X25]

  (930) 0x431c84 ADD	X25, X20, X23

  (930) 0x431c88 ADD	X23, X23, #32

  (930) 0x431c8c FMLA	V17.2D, V19.2D, V7.D[0]

  (930) 0x431c90 FMLA	V18.2D, V20.2D, V7.D[0]

  (930) 0x431c94 LDP	Q19, Q20, [X25]

  (930) 0x431c98 FMLA	V20.2D, V17.2D, V16.D[0]

  (930) 0x431c9c FMLA	V19.2D, V18.2D, V16.D[0]

  (930) 0x431ca0 STP	Q19, Q20, [X25]

  (930) 0x431ca4 B.NE	431c48

0x431ca8 ORR	X25, XZR, X9

0x431cac CMP	X9, X19

0x431cb0 B.EQ	431900

  (936) 0x431cb4 UBFM	X30, X25, #61, #60

  (936) 0x431cb8 ORR	X23, XZR, XZR

  (936) 0x431cbc SUB	X24, X19, X25

  (936) 0x431cc0 ADD	X25, X20, X30

  (936) 0x431cc4 ADD	X26, X21, X30

  (936) 0x431cc8 ADD	X27, X7, X30

  (936) 0x431ccc ADD	X28, X6, X30

  (936) 0x431cd0 ADD	X30, X5, X30

  (936) 0x431cd4 HINT	#0

  (936) 0x431cd8 HINT	#0

  (936) 0x431cdc HINT	#0

    (935) 0x431ce0 LDR	D17, [X30, X23,LSL #3]

    (935) 0x431ce4 LDR	D18, [X28, X23,LSL #3]

    (935) 0x431ce8 FMUL	D17, D17, D4

    (935) 0x431cec FMADD	D17, D18, D5, D17

    (935) 0x431cf0 LDR	D18, [X27, X23,LSL #3]

    (935) 0x431cf4 FMADD	D17, D18, D6, D17

    (935) 0x431cf8 LDR	D18, [X26, X23,LSL #3]

    (935) 0x431cfc FMADD	D17, D7, D18, D17

    (935) 0x431d00 LDR	D18, [X25, X23,LSL #3]

    (935) 0x431d04 FMADD	D17, D16, D17, D18

    (935) 0x431d08 STR	D17, [X25, X23,LSL #3]

    (935) 0x431d0c ADD	X23, X23, #1

    (935) 0x431d10 CMP	X24, X23

    (935) 0x431d14 B.NE	431ce0

  (936) 0x431d18 B	431900

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 65 - 74

--------------------------------------------------------------------------------

65:   for (size_t i = 0; i < 4; i++)

66:     for (size_t j = 0; j < 4; j++)

67:     {

68:       const T pre00           = a[i] * b[j];

69:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

70: #pragma omp simd aligned(coefs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_)

71:       for (size_t n = 0; n < num_splines; n++)

72:         vals[n] += pre00 *

73:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

74:              c[3] * coefs[n + 3 * zs]);

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:175	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:194	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:485	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P2, P3, P4, P5,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:70-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P2, P3, P4, P5,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:70-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:65-74
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:65-74.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:70-71.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 431c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X24, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.EQ 431900 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x360>	1	0.50	0.50	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:65-74
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:65-74.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:70-71.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 431c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X24, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.EQ 431900 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x360>	1	0.50	0.50	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code