OV - exec - Loop 932

0x431a68 ADD	X25, X16, X23

0x431a6c SUBS	X24, X24, #4

0x431a70 LDP	Q19, Q18, [X25]    [3]

0x431a74 ADD	X25, X17, X23

0x431a78 LDP	Q21, Q20, [X25]    [5]

0x431a7c ADD	X25, X18, X23

0x431a80 FMUL	V18.2D, V18.2D, V4.D[0]

0x431a84 FMUL	V19.2D, V19.2D, V4.D[0]

0x431a88 FMLA	V18.2D, V20.2D, V5.D[0]

0x431a8c FMLA	V19.2D, V21.2D, V5.D[0]

0x431a90 LDP	Q20, Q21, [X25]    [4]

0x431a94 ADD	X25, X0, X23

0x431a98 FMLA	V18.2D, V21.2D, V6.D[0]

0x431a9c FMLA	V19.2D, V20.2D, V6.D[0]

0x431aa0 LDP	Q21, Q20, [X25]    [2]

0x431aa4 ADD	X25, X20, X23

0x431aa8 ADD	X23, X23, #32

0x431aac FMLA	V18.2D, V20.2D, V7.D[0]

0x431ab0 FMLA	V19.2D, V21.2D, V7.D[0]

0x431ab4 LDP	Q20, Q21, [X25]    [1]

0x431ab8 FMLA	V21.2D, V18.2D, V17.D[0]

0x431abc FMLA	V20.2D, V19.2D, V17.D[0]

0x431ac0 STP	Q20, Q21, [X25]    [1]

0x431ac4 B.NE	431a68

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 71 - 74

--------------------------------------------------------------------------------

71:       for (size_t n = 0; n < num_splines; n++)

72:         vals[n] += pre00 *

73:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

74:              c[3] * coefs[n + 3 * zs]);

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:175	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:194	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:485	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:71-74
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.00
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.56
CQA cycles if fully vectorized	2.28
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	2.75
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.17
P10 cycles	1.83
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:71-74
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.00
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.56
CQA cycles if fully vectorized	2.28
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	2.75
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.17
P10 cycles	1.83
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.18
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:71-74
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:71-74.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.75 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 66% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 2.28 cycles (1.32x speedup).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
20: multiply (16 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431a68

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X25, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X24, X24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q19, Q18, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q21, Q20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V18.2D, V18.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V19.2D, V19.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V18.2D, V20.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V21.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q20, Q21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V18.2D, V21.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V20.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q21, Q20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V18.2D, V20.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V21.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q20, Q21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V21.2D, V18.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V19.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q20, Q21, [X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 431a68 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:71-74
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:71-74.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.75 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 66% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 2.28 cycles (1.32x speedup).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 16 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
20: multiply (16 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431a68

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X25, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X24, X24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP Q19, Q18, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP Q21, Q20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL V18.2D, V18.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL V19.2D, V19.2D, V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V18.2D, V20.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V21.2D, V5.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q20, Q21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V18.2D, V21.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V20.2D, V6.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q21, Q20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X25, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMLA V18.2D, V20.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V19.2D, V21.2D, V7.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP Q20, Q21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
FMLA V21.2D, V18.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMLA V20.2D, V19.2D, V17.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP Q20, Q21, [X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 431a68 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code