OV - exec - Loop 319

	Loop Id: 319	Module: exec	Source: BsplineFunctor.h:303-336	Coverage: 0.08%

0x416ac0 LD1D	{Z23.D}, P0/Z, [X12, X16,LSL #3]    [17]

0x416ac4 ADD	X29, SP, #304

0x416ac8 LD1SW	{Z24.D}, P0/Z, [X13, X16,LSL #2]    [13]

0x416acc ADD	X16, X16, X15

0x416ad0 CMP	X17, X16

0x416ad4 FMUL	Z25.D, Z23.D, Z7.D

0x416ad8 MOVPRFX	Z26, Z25

0x416adc FCVTZS	Z26.D, P0/M, Z25.D

0x416ae0 MOVPRFX	Z27, Z26

0x416ae4 SCVTF	Z27.D, P0/M, Z26.D

0x416ae8 LD1D	{Z29.D}, P0/Z, [X11, Z26.D,LSL #3]    [8]

0x416aec MOVPRFX	Z30, Z26

0x416af0 ADD	Z30.D, Z30.D, #1

0x416af4 MOVPRFX	Z31, Z26

0x416af8 ADD	Z31.D, Z31.D, #2

0x416afc LD1D	{Z30.D}, P0/Z, [X11, Z30.D,SXTW #3]    [20]

0x416b00 LD1D	{Z31.D}, P0/Z, [X11, Z31.D,SXTW #3]    [4]

0x416b04 ADD	Z26.D, Z26.D, #3

0x416b08 LDR	Z8, [X29, #19, MUL VL]    [21]

0x416b0c ADD	X29, SP, #304

0x416b10 LDR	Z9, [X29, #18, MUL VL]    [6]

0x416b14 ADD	X29, SP, #304

0x416b18 LDR	Z10, [X29, #17, MUL VL]    [28]

0x416b1c ADD	X29, SP, #304

0x416b20 FSUB	Z25.D, Z25.D, Z27.D

0x416b24 FMUL	Z27.D, Z25.D, Z25.D

0x416b28 FMLA	Z8.D, P0/M, Z0.D, Z25.D

0x416b2c FMAD	Z9.D, P0/M, Z25.D, Z10.D

0x416b30 LDR	Z10, [X29, #11, MUL VL]    [10]

0x416b34 ADD	X29, SP, #304

0x416b38 FMUL	Z28.D, Z27.D, Z25.D

0x416b3c LDR	Z11, [X29, #9, MUL VL]    [16]

0x416b40 ADD	X29, SP, #304

0x416b44 FMUL	Z8.D, Z8.D, Z29.D

0x416b48 FMLA	Z8.D, P0/M, Z9.D, Z30.D

0x416b4c FMAD	Z10.D, P0/M, Z27.D, Z11.D

0x416b50 LDR	Z11, [X29, #10, MUL VL]    [9]

0x416b54 ADD	X29, SP, #304

0x416b58 FMLA	Z10.D, P0/M, Z11.D, Z25.D

0x416b5c LDR	Z11, [X29, #8, MUL VL]    [27]

0x416b60 ADD	X29, SP, #304

0x416b64 LDR	Z9, [X29, #7, MUL VL]    [24]

0x416b68 ADD	X29, SP, #304

0x416b6c LD1D	{Z26.D}, P0/Z, [X11, Z26.D,SXTW #3]    [5]

0x416b70 FMUL	Z10.D, Z10.D, Z29.D

0x416b74 FMAD	Z11.D, P0/M, Z27.D, Z12.D

0x416b78 FMAD	Z9.D, P0/M, Z25.D, Z11.D

0x416b7c FMAD	Z9.D, P0/M, Z30.D, Z10.D

0x416b80 MOVPRFX	Z10, Z1

0x416b84 FMLA	Z10.D, P0/M, Z13.D, Z28.D

0x416b88 FMLA	Z10.D, P0/M, Z14.D, Z27.D

0x416b8c FMLA	Z10.D, P0/M, Z15.D, Z25.D

0x416b90 FMUL	Z29.D, Z10.D, Z29.D

0x416b94 MOVPRFX	Z10, Z5

0x416b98 FMLA	Z10.D, P0/M, Z2.D, Z28.D

0x416b9c FMLA	Z10.D, P0/M, Z3.D, Z27.D

0x416ba0 FMLA	Z10.D, P0/M, Z4.D, Z25.D

0x416ba4 FMLA	Z29.D, P0/M, Z10.D, Z30.D

0x416ba8 LDR	Z30, [X29, #16, MUL VL]    [11]

0x416bac ADD	X29, SP, #304

0x416bb0 LDR	Z10, [X29, #15, MUL VL]    [12]

0x416bb4 ADD	X29, SP, #304

0x416bb8 FMAD	Z30.D, P0/M, Z25.D, Z10.D

0x416bbc FMAD	Z30.D, P0/M, Z31.D, Z8.D

0x416bc0 LDR	Z8, [X29, #5, MUL VL]    [23]

0x416bc4 ADD	X29, SP, #304

0x416bc8 LDR	Z10, [X29, #3, MUL VL]    [7]

0x416bcc ADD	X29, SP, #304

0x416bd0 FMAD	Z8.D, P0/M, Z27.D, Z10.D

0x416bd4 LDR	Z10, [X29, #4, MUL VL]    [3]

0x416bd8 ADD	X29, SP, #304

0x416bdc FMLA	Z8.D, P0/M, Z10.D, Z25.D

0x416be0 FMAD	Z8.D, P0/M, Z31.D, Z9.D

0x416be4 MOVPRFX	Z9, Z18

0x416be8 FMLA	Z9.D, P0/M, Z6.D, Z28.D

0x416bec FMLA	Z9.D, P0/M, Z16.D, Z27.D

0x416bf0 FMAD	Z28.D, P0/M, Z19.D, Z22.D

0x416bf4 FMLA	Z9.D, P0/M, Z17.D, Z25.D

0x416bf8 FMLA	Z29.D, P0/M, Z9.D, Z31.D

0x416bfc LDR	Z31, [X29, #14, MUL VL]    [26]

0x416c00 ADD	X29, SP, #304

0x416c04 LDR	Z9, [X29, #13, MUL VL]    [19]

0x416c08 ADD	X29, SP, #304

0x416c0c FMAD	Z31.D, P0/M, Z25.D, Z9.D

0x416c10 FMLA	Z30.D, P0/M, Z31.D, Z26.D

0x416c14 LDR	Z31, [X29, #2, MUL VL]    [1]

0x416c18 ADD	X29, SP, #304

0x416c1c LDR	Z9, [X29, MUL VL]    [15]

0x416c20 ADD	X29, SP, #304

0x416c24 FMAD	Z31.D, P0/M, Z27.D, Z9.D

0x416c28 LDR	Z9, [X29, #1, MUL VL]    [22]

0x416c2c FMAD	Z27.D, P0/M, Z20.D, Z28.D

0x416c30 ADD	X29, SP, #304

0x416c34 FMLA	Z31.D, P0/M, Z9.D, Z25.D

0x416c38 FMAD	Z25.D, P0/M, Z21.D, Z27.D

0x416c3c LDR	Z27, [X29, #12, MUL VL]    [2]

0x416c40 FMAD	Z31.D, P0/M, Z26.D, Z8.D

0x416c44 FMAD	Z25.D, P0/M, Z26.D, Z29.D

0x416c48 FMUL	Z27.D, Z27.D, Z30.D

0x416c4c FMUL	Z26.D, Z31.D, Z7.D

0x416c50 ST1D	{Z27.D}, P0, [X10, Z24.D,LSL #3]    [25]

0x416c54 FDIVR	Z23.D, P0/M, Z23.D, Z26.D

0x416c58 ST1D	{Z23.D}, P0, [X9, Z24.D,LSL #3]    [18]

0x416c5c ST1D	{Z25.D}, P0, [X8, Z24.D,LSL #3]    [14]

0x416c60 B.NE	416ac0

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 303 - 336

--------------------------------------------------------------------------------

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P6, P7,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:303-336
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.50
CQA cycles if no scalar integer	27.50
CQA cycles if FP arith vectorized	27.50
CQA cycles if fully vectorized	27.50
Front-end cycles	13.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	27.50
P6 cycles	27.50
P7 cycles	21.00
P8 cycles	21.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	11.05
Nb FLOP add-sub	4.00
Nb FLOP mul	32.00
Nb FLOP fma	132.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.58
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.48
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	99.11
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P6, P7,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:303-336
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.50
CQA cycles if no scalar integer	27.50
CQA cycles if FP arith vectorized	27.50
CQA cycles if fully vectorized	27.50
Front-end cycles	13.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	27.50
P6 cycles	27.50
P7 cycles	21.00
P8 cycles	21.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	11.05
Nb FLOP add-sub	4.00
Nb FLOP mul	32.00
Nb FLOP fma	132.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.58
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.48
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	99.11
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:303-336
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:303-336.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 99% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences
SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
164: multiply (132 inside FMA instructions)
4: divide

The binary loop is loading 800 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.34 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.25	5.25	5.25	5.25	27.50	27.50	1.50	1.50	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	5.25	5.25	5.25	5.25	27.50	27.50	21.00	21.00	14.00	14.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.13
Data deps.	1.00
Overall L1	27.50

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.50 cycles. At this rate:

30% of peak load performance is reached (29.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 416ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P0/Z, [X12, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1SW {Z24.D}, P0/Z, [X13, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
FMUL Z25.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z26.D, P0/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z27.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
LD1D {Z29.D}, P0/Z, [X11, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [X11, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X11, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z26.D, Z26.D, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z8, [X29, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FSUB Z25.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z25.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z10, [X29, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z28.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z11, [X29, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z8.D, Z8.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z10.D, P0/M, Z27.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z11, [X29, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z10.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z11, [X29, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z26.D}, P0/Z, [X11, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z11.D, P0/M, Z27.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z25.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z10, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z10.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z14.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z15.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z10.D, P0/M, Z2.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z30, [X29, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z30.D, P0/M, Z25.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z30.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z8, [X29, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z8.D, P0/M, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z10, [X29, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z8.D, P0/M, Z10.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z8.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z9, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z9.D, P0/M, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z28.D, P0/M, Z19.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z9.D, P0/M, Z17.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X29, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z31.D, P0/M, Z25.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z30.D, P0/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X29, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z31.D, P0/M, Z27.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z9, [X29, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P0/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z9.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X29, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z31.D, P0/M, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z31.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z27.D}, P0, [X10, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FDIVR Z23.D, P0/M, Z23.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z23.D}, P0, [X9, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z25.D}, P0, [X8, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 416ac0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:303-336
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 99% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 132 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences
SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (132 inside FMA instructions)
164: multiply (132 inside FMA instructions)
4: divide

The binary loop is loading 800 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.34 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.25	5.25	5.25	5.25	27.50	27.50	1.50	1.50	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	5.25	5.25	5.25	5.25	27.50	27.50	21.00	21.00	14.00	14.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.13
Data deps.	1.00
Overall L1	27.50

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.50 cycles. At this rate:

30% of peak load performance is reached (29.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 416ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P0/Z, [X12, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1SW {Z24.D}, P0/Z, [X13, X16,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
FMUL Z25.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCVTZS Z26.D, P0/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SCVTF Z27.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
LD1D {Z29.D}, P0/Z, [X11, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z30, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z31.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [X11, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X11, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z26.D, Z26.D, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z8, [X29, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FSUB Z25.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z25.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z10, [X29, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z28.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LDR Z11, [X29, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z8.D, Z8.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z10.D, P0/M, Z27.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z11, [X29, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z10.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z11, [X29, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z26.D}, P0/Z, [X11, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z11.D, P0/M, Z27.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z25.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z9.D, P0/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z10, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z10.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z14.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z15.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z10.D, P0/M, Z2.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z10.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z30, [X29, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z30.D, P0/M, Z25.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z30.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z8, [X29, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z10, [X29, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z8.D, P0/M, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z10, [X29, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z8.D, P0/M, Z10.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z8.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z9, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z9.D, P0/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z9.D, P0/M, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z28.D, P0/M, Z19.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z9.D, P0/M, Z17.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z29.D, P0/M, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X29, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z31.D, P0/M, Z25.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z30.D, P0/M, Z31.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z31, [X29, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z9, [X29, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMAD Z31.D, P0/M, Z27.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z9, [X29, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P0/M, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z31.D, P0/M, Z9.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z27, [X29, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z31.D, P0/M, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z25.D, P0/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z31.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z27.D}, P0, [X10, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FDIVR Z23.D, P0/M, Z23.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z23.D}, P0, [X9, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z25.D}, P0, [X8, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 416ac0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code