OV - exec - Loop 306

0x416080 ST1B	{Z0.B}, P0, [X25, X8]    [1]

0x416084 INCP	X8, P0.B

0x416088 WHILELO	P0.B, X8, X2

0x41608c B.MI	416080

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h: 257 - 257

--------------------------------------------------------------------------------

257: 	  ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

Coverage (%)	Name	Source Location	Module
►90.00+	qmcplusplus::DistanceTableAA<d[...]	DistanceTableAA.h:55	exec
○	qmcplusplus::createDistanceTab[...]	ostream:611	exec
○	qmcplusplus::ParticleSet::addT[...]	vector.tcc:112	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:79	exec
○	.omp_outlined.	miniqmc.cpp:389	exec
○	__kmp_invoke_microtask		libomp.so
►10.00+	qmcplusplus::DistanceTableBA<d[...]	DistanceTableBA.h:51	exec
○	qmcplusplus::createDistanceTab[...]	ostream:611	exec
○	qmcplusplus::ParticleSet::addT[...]	vector.tcc:112	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:79	exec
○	.omp_outlined.	miniqmc.cpp:389	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.50
Bottlenecks
Function	std::vector >::_M_default_append(unsigned long)
Source	alloc_traits.h:257-257
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	5
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.50
Bottlenecks
Function	std::vector >::_M_default_append(unsigned long)
Source	alloc_traits.h:257-257
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	5
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	std::vector >::_M_default_append(unsigned long)
Source file and lines	alloc_traits.h:257-257
Module	exec

The loop is defined in /usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h:257.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 32 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	5.00

Cycles summary

Front-end	0.50
Data deps.	5.00
Overall L1	5.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 416080

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ST1B {Z0.B}, P0, [X25, X8]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCP X8, P0.B	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.B, X8, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.MI 416080 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	std::vector >::_M_default_append(unsigned long)
Source file and lines	alloc_traits.h:257-257
Module	exec

The loop is defined in /usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h:257.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 32 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	5.00

Cycles summary

Front-end	0.50
Data deps.	5.00
Overall L1	5.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 416080

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ST1B {Z0.B}, P0, [X25, X8]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCP X8, P0.B	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.B, X8, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.MI 416080 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code