OV - exec - Loop 1293

	Loop Id: 1293	Module: exec	Source: ParticleBConds.h:185-217 [...]	Coverage: 26.83%

0x449ee0 ADD	Z21.D, Z3.D, Z19.D

0x449ee4 MOVPRFX	Z20, Z21

0x449ee8 SXTW	Z20.D, P0/M, Z21.D

0x449eec CMPGT	P1.D, P0/Z, Z16.D, Z20.D

0x449ef0 LD1RD	{Z25.D}, P0/Z, [X0, #1]    [9]

0x449ef4 LD1RD	{Z26.D}, P0/Z, [X0, #4]    [9]

0x449ef8 LD1RD	{Z27.D}, P0/Z, [X0, #7]    [9]

0x449efc LD1RD	{Z28.D}, P0/Z, [X0, #10]    [9]

0x449f00 ADD	Z3.D, Z3.D, Z4.D

0x449f04 LD1RD	{Z29.D}, P0/Z, [X0, #11]    [9]

0x449f08 LD1RD	{Z30.D}, P0/Z, [X0, #17]    [9]

0x449f0c SUBS	W2, W2, W18

0x449f10 SMOV	X4, V21.S[0]

0x449f14 LD1D	{Z23.D}, P0/Z, [X10, X4,LSL #3]    [8]

0x449f18 LD1D	{Z21.D}, P0/Z, [X8, X4,LSL #3]    [3]

0x449f1c SEL	Z20.D, P1, Z18.D, Z17.D

0x449f20 LD1D	{Z22.D}, P0/Z, [X9, X4,LSL #3]    [4]

0x449f24 FSUB	Z23.D, Z23.D, Z7.D

0x449f28 FSUB	Z21.D, Z21.D, Z5.D

0x449f2c FSUB	Z22.D, Z22.D, Z6.D

0x449f30 FMUL	Z24.D, Z23.D, Z20.D

0x449f34 LD1RD	{Z23.D}, P0/Z, [X0]    [9]

0x449f38 FMUL	Z21.D, Z21.D, Z20.D

0x449f3c FMUL	Z22.D, Z22.D, Z20.D

0x449f40 FMUL	Z23.D, Z23.D, Z21.D

0x449f44 FMLA	Z23.D, P0/M, Z25.D, Z22.D

0x449f48 LD1RD	{Z25.D}, P0/Z, [X0, #2]    [9]

0x449f4c FMLA	Z23.D, P0/M, Z25.D, Z24.D

0x449f50 LD1RD	{Z25.D}, P0/Z, [X0, #3]    [9]

0x449f54 FRINTM	Z23.D, P0/M, Z23.D

0x449f58 FMUL	Z25.D, Z25.D, Z21.D

0x449f5c FMLA	Z25.D, P0/M, Z26.D, Z22.D

0x449f60 LD1RD	{Z26.D}, P0/Z, [X0, #5]    [9]

0x449f64 FMLA	Z25.D, P0/M, Z26.D, Z24.D

0x449f68 LD1RD	{Z26.D}, P0/Z, [X0, #6]    [9]

0x449f6c FRINTM	Z25.D, P0/M, Z25.D

0x449f70 FMUL	Z26.D, Z26.D, Z21.D

0x449f74 FMLA	Z26.D, P0/M, Z27.D, Z22.D

0x449f78 LD1RD	{Z27.D}, P0/Z, [X0, #8]    [9]

0x449f7c FMLA	Z26.D, P0/M, Z27.D, Z24.D

0x449f80 LD1RD	{Z27.D}, P0/Z, [X0, #9]    [9]

0x449f84 FRINTM	Z26.D, P0/M, Z26.D

0x449f88 FMUL	Z27.D, Z27.D, Z23.D

0x449f8c FMLA	Z27.D, P0/M, Z28.D, Z25.D

0x449f90 LD1RD	{Z28.D}, P0/Z, [X0, #12]    [9]

0x449f94 FMLA	Z27.D, P0/M, Z26.D, Z29.D

0x449f98 LD1RD	{Z29.D}, P0/Z, [X0, #14]    [9]

0x449f9c FMUL	Z28.D, Z28.D, Z23.D

0x449fa0 FSUB	Z21.D, Z21.D, Z27.D

0x449fa4 LD1RD	{Z27.D}, P0/Z, [X0, #13]    [9]

0x449fa8 FMAD	Z27.D, P0/M, Z25.D, Z28.D

0x449fac LD1RD	{Z28.D}, P0/Z, [X0, #15]    [9]

0x449fb0 FMLA	Z27.D, P0/M, Z29.D, Z26.D

0x449fb4 LD1RD	{Z29.D}, P0/Z, [X0, #16]    [9]

0x449fb8 FMUL	Z28.D, Z28.D, Z23.D

0x449fbc FSUB	Z23.D, Z22.D, Z27.D

0x449fc0 MOVPRFX	Z22, Z28

0x449fc4 FMLA	Z22.D, P0/M, Z29.D, Z25.D

0x449fc8 LD1RD	{Z25.D}, P0/Z, [X0, #19]    [9]

0x449fcc FMLA	Z22.D, P0/M, Z30.D, Z26.D

0x449fd0 LD1RD	{Z26.D}, P0/Z, [X0, #27]    [9]

0x449fd4 LD1RD	{Z27.D}, P0/Z, [X0, #35]    [9]

0x449fd8 LD1RD	{Z28.D}, P0/Z, [X0, #40]    [9]

0x449fdc FSUB	Z22.D, Z24.D, Z22.D

0x449fe0 FMUL	Z24.D, Z21.D, Z21.D

0x449fe4 FADD	Z25.D, Z25.D, Z21.D

0x449fe8 FADD	Z26.D, Z26.D, Z23.D

0x449fec FADD	Z27.D, Z27.D, Z22.D

0x449ff0 FADD	Z28.D, Z28.D, Z22.D

0x449ff4 FMLA	Z24.D, P0/M, Z23.D, Z23.D

0x449ff8 FMUL	Z25.D, Z25.D, Z25.D

0x449ffc FMLA	Z25.D, P0/M, Z26.D, Z26.D

0x44a000 LD1RD	{Z26.D}, P0/Z, [X0, #20]    [9]

0x44a004 FMLA	Z24.D, P0/M, Z22.D, Z22.D

0x44a008 FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a00c LD1RD	{Z27.D}, P0/Z, [X0, #28]    [9]

0x44a010 FADD	Z26.D, Z26.D, Z21.D

0x44a014 FCMGT	P1.D, P0/Z, Z24.D, Z25.D

0x44a018 FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a01c FMUL	Z26.D, Z26.D, Z26.D

0x44a020 FADD	Z25.D, Z27.D, Z23.D

0x44a024 LD1RD	{Z27.D}, P0/Z, [X0, #36]    [9]

0x44a028 FMAD	Z25.D, P0/M, Z25.D, Z26.D

0x44a02c LD1RD	{Z26.D}, P0/Z, [X0, #21]    [9]

0x44a030 FADD	Z27.D, Z27.D, Z22.D

0x44a034 FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a038 FADD	Z26.D, Z26.D, Z21.D

0x44a03c LD1RD	{Z27.D}, P0/Z, [X0, #37]    [9]

0x44a040 FMUL	Z26.D, Z26.D, Z26.D

0x44a044 FCMGT	P2.D, P0/Z, Z24.D, Z25.D

0x44a048 FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a04c LD1RD	{Z25.D}, P0/Z, [X0, #29]    [9]

0x44a050 FADD	Z27.D, Z27.D, Z22.D

0x44a054 FADD	Z25.D, Z25.D, Z23.D

0x44a058 FMAD	Z25.D, P0/M, Z25.D, Z26.D

0x44a05c LD1RD	{Z26.D}, P0/Z, [X0, #22]    [9]

0x44a060 FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a064 LD1RD	{Z27.D}, P0/Z, [X0, #38]    [9]

0x44a068 FCMGT	P3.D, P0/Z, Z24.D, Z25.D

0x44a06c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a070 FADD	Z25.D, Z26.D, Z21.D

0x44a074 LD1RD	{Z26.D}, P0/Z, [X0, #30]    [9]

0x44a078 FMUL	Z25.D, Z25.D, Z25.D

0x44a07c FADD	Z27.D, Z27.D, Z22.D

0x44a080 FADD	Z26.D, Z26.D, Z23.D

0x44a084 FMLA	Z25.D, P0/M, Z26.D, Z26.D

0x44a088 LD1RD	{Z26.D}, P0/Z, [X0, #31]    [9]

0x44a08c FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a090 LD1RD	{Z27.D}, P0/Z, [X0, #39]    [9]

0x44a094 FADD	Z26.D, Z26.D, Z23.D

0x44a098 FCMGT	P4.D, P0/Z, Z24.D, Z25.D

0x44a09c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a0a0 LD1RD	{Z25.D}, P0/Z, [X0, #23]    [9]

0x44a0a4 FADD	Z27.D, Z27.D, Z22.D

0x44a0a8 FADD	Z25.D, Z25.D, Z21.D

0x44a0ac FMUL	Z25.D, Z25.D, Z25.D

0x44a0b0 FMLA	Z25.D, P0/M, Z26.D, Z26.D

0x44a0b4 LD1RD	{Z26.D}, P0/Z, [X0, #24]    [9]

0x44a0b8 FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a0bc LD1RD	{Z27.D}, P0/Z, [X0, #32]    [9]

0x44a0c0 FADD	Z26.D, Z26.D, Z21.D

0x44a0c4 FCMGT	P5.D, P0/Z, Z24.D, Z25.D

0x44a0c8 FMUL	Z26.D, Z26.D, Z26.D

0x44a0cc FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a0d0 LD1RD	{Z25.D}, P0/Z, [X0, #25]    [9]

0x44a0d4 FADD	Z27.D, Z27.D, Z23.D

0x44a0d8 FMLA	Z26.D, P0/M, Z27.D, Z27.D

0x44a0dc LD1RD	{Z27.D}, P0/Z, [X0, #33]    [9]

0x44a0e0 FADD	Z25.D, Z25.D, Z21.D

0x44a0e4 FMLA	Z26.D, P0/M, Z28.D, Z28.D

0x44a0e8 LD1RD	{Z28.D}, P0/Z, [X0, #41]    [9]

0x44a0ec FMUL	Z25.D, Z25.D, Z25.D

0x44a0f0 FADD	Z27.D, Z27.D, Z23.D

0x44a0f4 FMLA	Z25.D, P0/M, Z27.D, Z27.D

0x44a0f8 FCMGT	P6.D, P0/Z, Z24.D, Z26.D

0x44a0fc FMINNM	Z24.D, P0/M, Z24.D, Z26.D

0x44a100 FADD	Z28.D, Z28.D, Z22.D

0x44a104 FMLA	Z25.D, P0/M, Z28.D, Z28.D

0x44a108 FCMGT	P7.D, P0/Z, Z24.D, Z25.D

0x44a10c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

0x44a110 CPY	Z25.D, P1/Z, #1

0x44a114 FSQRT	Z24.D, P0/M, Z24.D

0x44a118 CPY	Z25.D, P2/M, #2

0x44a11c CPY	Z25.D, P3/M, #3

0x44a120 CPY	Z25.D, P4/M, #4

0x44a124 CPY	Z25.D, P5/M, #5

0x44a128 CPY	Z25.D, P6/M, #6

0x44a12c CPY	Z25.D, P7/M, #7

0x44a130 ST1D	{Z24.D}, P0, [X3, X4,LSL #3]    [11]

0x44a134 LD1D	{Z24.D}, P0/Z, [X14, Z25.D,LSL #3]    [6]

0x44a138 FADD	Z21.D, Z24.D, Z21.D

0x44a13c FMUL	Z21.D, Z21.D, Z20.D

0x44a140 ST1D	{Z21.D}, P0, [X11, X4,LSL #3]    [1]

0x44a144 LD1D	{Z21.D}, P0/Z, [X15, Z25.D,LSL #3]    [2]

0x44a148 FADD	Z21.D, Z21.D, Z23.D

0x44a14c FMUL	Z21.D, Z21.D, Z20.D

0x44a150 ST1D	{Z21.D}, P0, [X12, X4,LSL #3]    [10]

0x44a154 LD1D	{Z21.D}, P0/Z, [X16, Z25.D,LSL #3]    [7]

0x44a158 FADD	Z21.D, Z21.D, Z22.D

0x44a15c FMUL	Z20.D, Z21.D, Z20.D

0x44a160 ST1D	{Z20.D}, P0, [X13, X4,LSL #3]    [5]

0x44a164 B.NE	449ee0

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 177 - 177

--------------------------------------------------------------------------------

177:   inline const Type_t& operator[](unsigned int i) const { return X[i]; }

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h: 185 - 217

--------------------------------------------------------------------------------

185: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

186:     for (int iat = first; iat < last; ++iat)

187:     {

188:       const T flip    = iat < flip_ind ? one : minusone;

189:       const T displ_0 = (px[iat] - x0) * flip;

190:       const T displ_1 = (py[iat] - y0) * flip;

191:       const T displ_2 = (pz[iat] - z0) * flip;

192:

193:       const T ar_0 = -std::floor(displ_0 * g00 + displ_1 * g10 + displ_2 * g20);

194:       const T ar_1 = -std::floor(displ_0 * g01 + displ_1 * g11 + displ_2 * g21);

195:       const T ar_2 = -std::floor(displ_0 * g02 + displ_1 * g12 + displ_2 * g22);

196:

197:       const T delx = displ_0 + ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

198:       const T dely = displ_1 + ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

199:       const T delz = displ_2 + ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

200:

201:       T rmin = delx * delx + dely * dely + delz * delz;

[...]

209:         const T r2 = x * x + y * y + z * z;

210:         ic         = (r2 < rmin) ? c : ic;

211:         rmin       = (r2 < rmin) ? r2 : rmin;

212:       }

213:

214:       temp_r[iat] = std::sqrt(rmin);

215:       dx[iat]     = flip * (delx + cellx[ic]);

216:       dy[iat]     = flip * (dely + celly[ic]);

217:       dz[iat]     = flip * (delz + cellz[ic]);

Coverage (%)	Name	Source Location	Module
►78.79+	.omp_outlined..62	miniqmc.cpp:482	exec
○	__kmp_invoke_microtask		libomp.so
►15.15+	qmcplusplus::ParticleSet::setA[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:425	exec
○	__kmp_invoke_microtask		libomp.so
►3.03+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:919	exec
○	.omp_outlined.	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
►3.03+	.omp_outlined..62	miniqmc.cpp:432	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P6, P7,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	TinyVector.h:177-177,ParticleBConds.h:185-201,ParticleBConds.h:209-217
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	55.00
CQA cycles if no scalar integer	55.00
CQA cycles if FP arith vectorized	55.00
CQA cycles if fully vectorized	51.61
Front-end cycles	20.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	55.00
P6 cycles	55.00
P7 cycles	39.00
P8 cycles	39.00
P9 cycles	24.50
P10 cycles	24.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	162.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	7.78
Nb FLOP add-sub	120.00
Nb FLOP mul	80.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.49
Bytes prefetched	0.00
Bytes loaded	504.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	69.38
Vectorization ratio load	13.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.97
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	68.97
Vector-efficiency ratio all	76.93
Vector-efficiency ratio load	35.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.35
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	76.62

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P6, P7,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	TinyVector.h:177-177,ParticleBConds.h:185-201,ParticleBConds.h:209-217
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	55.00
CQA cycles if no scalar integer	55.00
CQA cycles if FP arith vectorized	55.00
CQA cycles if fully vectorized	51.61
Front-end cycles	20.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	55.00
P6 cycles	55.00
P7 cycles	39.00
P8 cycles	39.00
P9 cycles	24.50
P10 cycles	24.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	162.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	7.78
Nb FLOP add-sub	120.00
Nb FLOP mul	80.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.49
Bytes prefetched	0.00
Bytes loaded	504.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	69.38
Vectorization ratio load	13.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	96.97
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	68.97
Vector-efficiency ratio all	76.93
Vector-efficiency ratio load	35.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	97.35
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	76.62

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds.h:185-217
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:185-201,209-217

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 55.00 to 51.61 cycles (1.07x speedup).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

13% of VPU loads are used in vector version.
96% of VPU addition or subtraction instructions are used in vector version.
68% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 428 FP arithmetical operations:

232: addition or subtraction (112 inside FMA instructions)
192: multiply (112 inside FMA instructions)
4: square root

The binary loop is loading 504 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.68 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	55.00	55.00	2.50	2.50	24.50	24.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	55.00	55.00	39.00	39.00	24.50	24.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.25
Data deps.	1.00
Overall L1	55.00

Vectorization ratios

INT

all	23%
load	13%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	69%
load	13%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	68%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.00 cycles. At this rate:

9% of peak load performance is reached (9.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD Z21.D, Z3.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
CMPGT P1.D, P0/Z, Z16.D, Z20.D	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1
LD1RD {Z25.D}, P0/Z, [X0, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z26.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z29.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z30.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUBS W2, W2, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SMOV X4, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	1
LD1D {Z23.D}, P0/Z, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z20.D, P1, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P0/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z21.D, Z21.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z22.D, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z23.D}, P0/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z22.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z23.D, P0/M, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z23.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z26.D, P0/M, Z27.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z27.D, P0/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P0/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z29.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z21.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P0/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P0/M, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z29.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z23.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z22.D, P0/M, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z22.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X0, #35]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P0/M, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z24.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGT P3.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z26.D}, P0/Z, [X0, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #31]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #39]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P6.D, P0/Z, Z24.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P7.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P1/Z, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
CPY Z25.D, P2/M, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P3/M, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P4/M, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P5/M, #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P6/M, #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P7/M, #7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P0, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z24.D}, P0/Z, [X14, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z21.D}, P0, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X15, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z21.D}, P0, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z20.D}, P0, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 449ee0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds.h:185-217
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:185-201,209-217

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

13% of VPU loads are used in vector version.
96% of VPU addition or subtraction instructions are used in vector version.
68% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 428 FP arithmetical operations:

232: addition or subtraction (112 inside FMA instructions)
192: multiply (112 inside FMA instructions)
4: square root

The binary loop is loading 504 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.68 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	55.00	55.00	2.50	2.50	24.50	24.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	55.00	55.00	39.00	39.00	24.50	24.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.25
Data deps.	1.00
Overall L1	55.00

Vectorization ratios

INT

all	23%
load	13%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	69%
load	13%
store	100%
mul	100%
add-sub	96%
fma	100%
div/sqrt	100%
other	68%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.00 cycles. At this rate:

9% of peak load performance is reached (9.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD Z21.D, Z3.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
CMPGT P1.D, P0/Z, Z16.D, Z20.D	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1
LD1RD {Z25.D}, P0/Z, [X0, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z26.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z29.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z30.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUBS W2, W2, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SMOV X4, V21.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	1
LD1D {Z23.D}, P0/Z, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z20.D, P1, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P0/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z21.D, Z21.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z22.D, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z23.D}, P0/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z22.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z23.D, P0/M, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z23.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z26.D, P0/M, Z27.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FRINTM Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FMUL Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z27.D, P0/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P0/M, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z29.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z21.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z27.D, P0/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z27.D, P0/M, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z29.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z23.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z22.D, P0/M, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z25.D}, P0/Z, [X0, #19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z22.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X0, #35]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z28.D}, P0/Z, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P0/M, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z24.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z25.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z27.D}, P0/Z, [X0, #37]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P2.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #29]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #38]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGT P3.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z26.D}, P0/Z, [X0, #30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #31]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #39]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z25.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z26.D}, P0/Z, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z25.D}, P0/Z, [X0, #25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z27.D}, P0/Z, [X0, #33]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z25.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z28.D}, P0/Z, [X0, #41]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P6.D, P0/Z, Z24.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z25.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMGT P7.D, P0/Z, Z24.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z24.D, P0/M, Z24.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P1/Z, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
CPY Z25.D, P2/M, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P3/M, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P4/M, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P5/M, #5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P6/M, #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
CPY Z25.D, P7/M, #7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P0, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z24.D}, P0/Z, [X14, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z21.D}, P0, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X15, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z21.D}, P0, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P0/Z, [X16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z20.D}, P0, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 449ee0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code