OV - exec - Function qmcplusplus::DTD_BConds<double, 3u, 39>::computeDistancesOffload(double const*, double const*, int, double*, double*, int, int, int) const

	Function: qmcplusplus::DTD_BConds<double, 3u, 39>::computeDistancesOffload(double const*, double con ...	Module: exec	Source: ParticleBConds.h:230-279 [...]	Coverage: 0.12%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h: 230 - 279

--------------------------------------------------------------------------------

230:     const T x0 = pos[0];

231:     const T y0 = pos[1];

232:     const T z0 = pos[2];

233:

234:     const T* restrict px = R0;

235:     const T* restrict py = R0 + r0_stride;

236:     const T* restrict pz = R0 + r0_stride * 2;

237:

238:     T* restrict dx = temp_dr;

239:     T* restrict dy = temp_dr + padded_size;

240:     T* restrict dz = temp_dr + padded_size * 2;

241:

242:     const auto& cellx = corners[0];

[...]

249:     const T flip    = iat < flip_ind ? one : minusone;

250:     const T displ_0 = (px[iat] - x0) * flip;

251:     const T displ_1 = (py[iat] - y0) * flip;

252:     const T displ_2 = (pz[iat] - z0) * flip;

253:

254:     const T ar_0 = -std::floor(displ_0 * g00 + displ_1 * g10 + displ_2 * g20);

255:     const T ar_1 = -std::floor(displ_0 * g01 + displ_1 * g11 + displ_2 * g21);

256:     const T ar_2 = -std::floor(displ_0 * g02 + displ_1 * g12 + displ_2 * g22);

257:

258:     const T delx = displ_0 + ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

259:     const T dely = displ_1 + ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

260:     const T delz = displ_2 + ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

261:

262:     T rmin = delx * delx + dely * dely + delz * delz;

263:     int ic = 0;

264: #pragma unroll(7)

265:     for (int c = 1; c < 8; ++c)

266:     {

267:       const T x  = delx + cellx[c];

268:       const T y  = dely + celly[c];

269:       const T z  = delz + cellz[c];

270:       const T r2 = x * x + y * y + z * z;

271:       ic         = (r2 < rmin) ? c : ic;

272:       rmin       = (r2 < rmin) ? r2 : rmin;

273:     }

274:

275:     temp_r[iat] = std::sqrt(rmin);

276:     dx[iat]     = flip * (delx + cellx[ic]);

277:     dy[iat]     = flip * (dely + celly[ic]);

278:     dz[iat]     = flip * (delz + cellz[ic]);

279:   }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 177 - 177

--------------------------------------------------------------------------------

177:   inline const Type_t& operator[](unsigned int i) const { return X[i]; }

0x44ad10 SBFM	X8, X7, #61, #31

0x44ad14 LDP	D2, D3, [X1]

0x44ad18 LDR	W10, [SP]

0x44ad1c FMOV	D0, #-1.0000000

0x44ad20 FMOV	D6, #1.0000000

0x44ad24 SBFM	X11, X3, #60, #31

0x44ad28 LDR	D4, [X1, #16]

0x44ad2c LDP	D17, D18, [X0, #16]

0x44ad30 ADD	X9, X2, X8

0x44ad34 LDP	D20, D21, [X0, #112]

0x44ad38 LDR	D22, [X0, #168]

0x44ad3c CMP	W7, W10

0x44ad40 LDR	D1, [X9]

0x44ad44 LDR	D5, [X9, X3,SXTW #3]

0x44ad48 LDR	D7, [X9, X11]

0x44ad4c LDR	D23, [X0, #232]

0x44ad50 MOVZ	W10, #2

0x44ad54 MOVZ	W11, #3

0x44ad58 FCSEL	D0, D6, D0, #11

0x44ad5c LDP	D6, D16, [X0]

0x44ad60 FSUB	D1, D1, S2

0x44ad64 FSUB	D2, D5, S3

0x44ad68 FSUB	D4, D7, S4

0x44ad6c FMUL	D1, D1, D0

0x44ad70 FMUL	D2, D2, D0

0x44ad74 FMUL	D3, D6, D1

0x44ad78 LDP	D5, D6, [X0, #32]

0x44ad7c FMUL	D7, D18, D1

0x44ad80 LDP	D18, D19, [X0, #48]

0x44ad84 FMADD	D16, D16, D2, D3

0x44ad88 FMUL	D3, D4, D0

0x44ad8c FMADD	D4, D5, D2, D7

0x44ad90 FMUL	D5, D18, D1

0x44ad94 FMADD	D7, D17, D3, D16

0x44ad98 LDP	D16, D17, [X0, #64]

0x44ad9c FMADD	D5, D19, D2, D5

0x44ada0 FMADD	D4, D6, D3, D4

0x44ada4 LDP	D6, D18, [X0, #96]

0x44ada8 FRINTM	D7, D7

0x44adac FMADD	D5, D16, D3, D5

0x44adb0 FMUL	D16, D17, D7

0x44adb4 FRINTM	D4, D4

0x44adb8 LDP	D17, D19, [X0, #80]

0x44adbc FMUL	D6, D6, D7

0x44adc0 FMUL	D7, D21, D7

0x44adc4 FRINTM	D5, D5

0x44adc8 FMADD	D6, D18, D4, D6

0x44adcc FMADD	D16, D17, D4, D16

0x44add0 LDP	D17, D18, [X0, #128]

0x44add4 FMADD	D6, D20, D5, D6

0x44add8 FMADD	D16, D5, D19, D16

0x44addc LDP	D19, D21, [X0, #152]

0x44ade0 FMADD	D4, D17, D4, D7

0x44ade4 LDP	Q20, Q17, [X0, #176]

0x44ade8 FSUB	D2, D2, S6

0x44adec FSUB	D1, D1, S16

0x44adf0 FADD	D23, D23, D2

0x44adf4 LDP	D7, D16, [X0, #216]

0x44adf8 FMADD	D4, D18, D5, D4

0x44adfc FADD	D19, D19, D1

0x44ae00 FADD	D22, D22, D1

0x44ae04 FADD	D6, D21, D1

0x44ae08 FMUL	D5, D1, D1

0x44ae0c FMUL	D18, D19, D19

0x44ae10 LDP	D19, D21, [X0, #280]

0x44ae14 FMUL	D22, D22, D22

0x44ae18 FMUL	D6, D6, D6

0x44ae1c FADD	D16, D16, D2

0x44ae20 FMADD	D5, D2, D2, D5

0x44ae24 FSUB	D3, D3, S4

0x44ae28 FADD	D4, D7, D2

0x44ae2c DUP	V7.2D, V1.D[0]

0x44ae30 FMADD	D22, D23, D23, D22

0x44ae34 DUP	V23.2D, V2.D[0]

0x44ae38 FMADD	D6, D16, D16, D6

0x44ae3c LDR	D16, [X0, #296]

0x44ae40 FADD	V20.2D, V20.2D, V7.2D

0x44ae44 FADD	V7.2D, V17.2D, V7.2D

0x44ae48 FMADD	D4, D4, D4, D18

0x44ae4c LDP	Q18, Q17, [X0, #240]

0x44ae50 FADD	D21, D21, D3

0x44ae54 FMADD	D5, D3, D3, D5

0x44ae58 FMUL	V20.2D, V20.2D, V20.2D

0x44ae5c FADD	D19, D19, D3

0x44ae60 FMUL	V7.2D, V7.2D, V7.2D

0x44ae64 FMADD	D6, D21, D21, D6

0x44ae68 DUP	V21.2D, V3.D[0]

0x44ae6c FMADD	D4, D19, D19, D4

0x44ae70 FADD	V17.2D, V17.2D, V23.2D

0x44ae74 FADD	D16, D16, D3

0x44ae78 FADD	V18.2D, V18.2D, V23.2D

0x44ae7c FMLA	V7.2D, V17.2D, V17.2D

0x44ae80 FMADD	D16, D16, D16, D22

0x44ae84 FMLA	V20.2D, V18.2D, V18.2D

0x44ae88 LDP	Q18, Q19, [X0, #304]

0x44ae8c FMINNM	D22, D4, D5

0x44ae90 FCMP	D4, D5

0x44ae94 FMINNM	D17, D6, D22

0x44ae98 CSINC	W9, WZR, WZR, #10

0x44ae9c FCMP	D6, D22

0x44aea0 CSEL	X9, X10, X9, #11

0x44aea4 FCMP	D16, D17

0x44aea8 FADD	V18.2D, V18.2D, V21.2D

0x44aeac CSEL	X9, X11, X9, #11

0x44aeb0 MOVZ	W11, #4

0x44aeb4 FMLA	V20.2D, V18.2D, V18.2D

0x44aeb8 FADD	V18.2D, V19.2D, V21.2D

0x44aebc FMINNM	D19, D16, D17

0x44aec0 FMLA	V7.2D, V18.2D, V18.2D

0x44aec4 MOV	D18, V20.D[1]

0x44aec8 FMINNM	D21, D20, D19

0x44aecc FMINNM	D18, D18, D21

0x44aed0 MOV	V19.D[1], V21.D[0]

0x44aed4 MOV	D5, V7.D[1]

0x44aed8 FMINNM	D23, D7, D18

0x44aedc MOV	V18.D[1], V23.D[0]

0x44aee0 FMINNM	D5, D5, D23

0x44aee4 FCMGT	V19.2D, V19.2D, V20.2D

0x44aee8 FCMGT	V18.2D, V18.2D, V7.2D

0x44aeec UZP1	V4.4S, V19.4S, V18.4S

0x44aef0 XTN	V4.4H, V4.4S

0x44aef4 UMOV	W10, V4.H[0]

0x44aef8 UMOV	W12, V4.H[1]

0x44aefc ANDS	WZR, W10, #0

0x44af00 UMOV	W10, V4.H[2]

0x44af04 CSEL	X9, X11, X9, #1

0x44af08 ANDS	WZR, W12, #0

0x44af0c UMOV	W12, V4.H[3]

0x44af10 FSQRT	D4, D5

0x44af14 MOVZ	W11, #5

0x44af18 CSEL	X9, X11, X9, #1

0x44af1c MOVZ	W11, #6

0x44af20 ANDS	WZR, W10, #0

0x44af24 MOVZ	W10, #7

0x44af28 CSEL	X9, X11, X9, #1

0x44af2c ANDS	WZR, W12, #0

0x44af30 ADD	X11, X5, X8

0x44af34 CSEL	X9, X10, X9, #1

0x44af38 SBFM	X10, X6, #60, #31

0x44af3c ADD	X9, X0, X9,LSL #3

0x44af40 STR	D4, [X4, X8]

0x44af44 LDR	D4, [X9, #144]

0x44af48 FADD	D1, D4, D1

0x44af4c FMUL	D1, D1, D0

0x44af50 STR	D1, [X11]

0x44af54 LDR	D1, [X9, #208]

0x44af58 FADD	D1, D1, D2

0x44af5c FMUL	D1, D1, D0

0x44af60 STR	D1, [X11, X6,SXTW #3]

0x44af64 LDR	D1, [X9, #272]

0x44af68 FADD	D1, D1, D3

0x44af6c FMUL	D0, D1, D0

0x44af70 STR	D0, [X11, X10]

0x44af74 RET

0x44af78 HINT	#0

0x44af7c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:919	exec
○	.omp_outlined.	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParticleBConds.h:230-279
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:230-242,249-279
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 10.00 cycles (2.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 40% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.50 to 22.37 cycles (1.14x speedup).

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

61% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
38% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 107 FP arithmetical operations:

58: addition or subtraction (28 inside FMA instructions)
48: multiply (28 inside FMA instructions)
1: square root

The binary function is loading 388 bytes. The binary function is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.00	6.00	6.00	6.00	25.50	25.50	25.50	25.50	10.33	10.33	10.33	0.00	0.00
cycles	0.50	0.50	6.00	6.00	6.00	6.00	25.50	25.50	25.50	25.50	10.33	10.33	10.33	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	19.25
Overall L1	25.50

Vectorization ratios

INT

all	45%
load	61%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	58%
load	61%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

15% of peak load performance is reached (15.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44ad10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SBFM X8, X7, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D2, D3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR W10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D6, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X11, X3, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D17, D18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X9, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D20, D21, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D22, [X0, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP W7, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X9, X3,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D23, [X0, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCSEL D0, D6, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDP D6, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D1, D1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D2, D5, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D4, D7, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D5, D6, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D7, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D18, D19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D16, D16, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D3, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D4, D5, D2, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D5, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D7, D17, D3, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D16, D17, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D5, D19, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D4, D6, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D6, D18, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FRINTM D7, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D16, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D16, D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FRINTM D4, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
LDP D17, D19, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D6, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D7, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FRINTM D5, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D18, D4, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D17, D4, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D17, D18, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D6, D20, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D5, D19, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D19, D21, [X0, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D4, D17, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q20, Q17, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FSUB D2, D2, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D1, D1, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D23, D23, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D7, D16, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D4, D18, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD D19, D19, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D22, D22, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D21, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D5, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D18, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D19, D21, [X0, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D22, D22, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D6, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D16, D16, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D5, D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FSUB D3, D3, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D4, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
DUP V7.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D22, D23, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
DUP V23.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D6, D16, D16, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D16, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD V20.2D, V20.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V7.2D, V17.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D4, D4, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q18, Q17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FADD D21, D21, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D5, D3, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL V20.2D, V20.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D19, D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL V7.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D6, D21, D21, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
DUP V21.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D4, D19, D19, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD V17.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D16, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V18.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMLA V7.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D16, D16, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMLA V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q18, Q19, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FMINNM D22, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D4, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMINNM D17, D6, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D6, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CSEL X9, X10, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FADD V18.2D, V18.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSEL X9, X11, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMLA V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD V18.2D, V19.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D19, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMLA V7.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
MOV D18, V20.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D21, D20, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D18, D18, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV V19.D[1], V21.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV D5, V7.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D23, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV V18.D[1], V23.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D5, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMGT V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMGT V18.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UZP1 V4.4S, V19.4S, V18.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
XTN V4.4H, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UMOV W10, V4.H[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
UMOV W12, V4.H[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
ANDS WZR, W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UMOV W10, V4.H[2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UMOV W12, V4.H[3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
FSQRT D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
MOVZ W11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ W10, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X11, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X10, X6, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D4, [X4, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X9, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D4, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X9, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X6,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X9, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	ParticleBConds.h:230-279
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:230-242,249-279
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

61% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
38% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 107 FP arithmetical operations:

58: addition or subtraction (28 inside FMA instructions)
48: multiply (28 inside FMA instructions)
1: square root

The binary function is loading 388 bytes. The binary function is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.00	6.00	6.00	6.00	25.50	25.50	25.50	25.50	10.33	10.33	10.33	0.00	0.00
cycles	0.50	0.50	6.00	6.00	6.00	6.00	25.50	25.50	25.50	25.50	10.33	10.33	10.33	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	19.25
Overall L1	25.50

Vectorization ratios

INT

all	45%
load	61%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	58%
load	61%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

15% of peak load performance is reached (15.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44ad10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SBFM X8, X7, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D2, D3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR W10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D6, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X11, X3, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D17, D18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X9, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D20, D21, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D22, [X0, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CMP W7, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR D1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X9, X3,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D23, [X0, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCSEL D0, D6, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
LDP D6, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D1, D1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D2, D5, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D4, D7, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D5, D6, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D7, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D18, D19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D16, D16, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D3, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D4, D5, D2, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D5, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D7, D17, D3, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D16, D17, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D5, D19, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D4, D6, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D6, D18, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FRINTM D7, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D16, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D16, D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FRINTM D4, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
LDP D17, D19, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D6, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D7, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FRINTM D5, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D18, D4, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D17, D4, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D17, D18, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D6, D20, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D5, D19, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D19, D21, [X0, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D4, D17, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q20, Q17, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FSUB D2, D2, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D1, D1, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D23, D23, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP D7, D16, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D4, D18, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD D19, D19, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D22, D22, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D21, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D5, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D18, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDP D19, D21, [X0, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D22, D22, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D6, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D16, D16, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D5, D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FSUB D3, D3, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D4, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
DUP V7.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D22, D23, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
DUP V23.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D6, D16, D16, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D16, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD V20.2D, V20.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V7.2D, V17.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D4, D4, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q18, Q17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FADD D21, D21, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D5, D3, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL V20.2D, V20.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D19, D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL V7.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D6, D21, D21, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
DUP V21.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D4, D19, D19, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD V17.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D16, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V18.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMLA V7.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D16, D16, D16, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMLA V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP Q18, Q19, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67
FMINNM D22, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D4, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMINNM D17, D6, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D6, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CSEL X9, X10, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FADD V18.2D, V18.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSEL X9, X11, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMLA V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD V18.2D, V19.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D19, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMLA V7.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
MOV D18, V20.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D21, D20, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D18, D18, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV V19.D[1], V21.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV D5, V7.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D23, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOV V18.D[1], V23.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D5, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMGT V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMGT V18.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UZP1 V4.4S, V19.4S, V18.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
XTN V4.4H, V4.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UMOV W10, V4.H[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
UMOV W12, V4.H[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
ANDS WZR, W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UMOV W10, V4.H[2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UMOV W12, V4.H[3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	1
FSQRT D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
MOVZ W11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ W10, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X11, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X10, X6, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D4, [X4, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X9, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D4, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X9, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X6,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X9, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
○qmcplusplus::DTD_BConds::computeDistancesOffload(double const, double const, int, double, double, int, int, int) const	0.12	0.06

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code