OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 39>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, 32ul, qmcplusplus::Mallocator<double, 32ul> >, qmcplusplus::VectorSoAContainer<double, 3u, 32ul, qmcplusplus::Mallocator<double, 32ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, 32ul, qmcplusplus::Mallocator<double, 32ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, 32ul, qmcplusplus::Mallocator<double, 32ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 39>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds.h:166-219 [...]	Coverage: 26.83%

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 177 - 177

--------------------------------------------------------------------------------

177:   inline const Type_t& operator[](unsigned int i) const { return X[i]; }

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h: 166 - 219

--------------------------------------------------------------------------------

166:   {

[...]

185: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

186:     for (int iat = first; iat < last; ++iat)

187:     {

188:       const T flip    = iat < flip_ind ? one : minusone;

189:       const T displ_0 = (px[iat] - x0) * flip;

190:       const T displ_1 = (py[iat] - y0) * flip;

191:       const T displ_2 = (pz[iat] - z0) * flip;

192:

193:       const T ar_0 = -std::floor(displ_0 * g00 + displ_1 * g10 + displ_2 * g20);

194:       const T ar_1 = -std::floor(displ_0 * g01 + displ_1 * g11 + displ_2 * g21);

195:       const T ar_2 = -std::floor(displ_0 * g02 + displ_1 * g12 + displ_2 * g22);

196:

197:       const T delx = displ_0 + ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

198:       const T dely = displ_1 + ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

199:       const T delz = displ_2 + ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

200:

201:       T rmin = delx * delx + dely * dely + delz * delz;

202:       int ic = 0;

203: #pragma unroll(7)

204:       for (int c = 1; c < 8; ++c)

205:       {

206:         const T x  = delx + cellx[c];

207:         const T y  = dely + celly[c];

208:         const T z  = delz + cellz[c];

209:         const T r2 = x * x + y * y + z * z;

210:         ic         = (r2 < rmin) ? c : ic;

211:         rmin       = (r2 < rmin) ? r2 : rmin;

212:       }

213:

214:       temp_r[iat] = std::sqrt(rmin);

215:       dx[iat]     = flip * (delx + cellx[ic]);

216:       dy[iat]     = flip * (dely + celly[ic]);

217:       dz[iat]     = flip * (delz + cellz[ic]);

218:     }

219:   }

0x449e40 STP	X22, X21, [SP, #992]!

0x449e44 STP	X20, X19, [SP, #16]

0x449e48 SUBS	W19, W6, W5

0x449e4c B.LE	44a3cc

0x449e50 LDP	D0, D1, [X1]

0x449e54 LDR	D2, [X1, #16]

0x449e58 LDR	X8, [X2, #24]

0x449e5c CNTD	X18, ALL

0x449e60 ORR	W17, WZR, WZR

0x449e64 ADD	X14, X0, #144

0x449e68 ADD	X15, X0, #208

0x449e6c ADD	X16, X0, #272

0x449e70 LDR	X10, [X2, #8]

0x449e74 LDR	X11, [X4, #24]

0x449e78 LDR	X13, [X4, #8]

0x449e7c CMP	W19, W18

0x449e80 ADD	X9, X8, X10,LSL #3

0x449e84 ADD	X10, X8, X10,LSL #4

0x449e88 ADD	X12, X11, X13,LSL #3

0x449e8c ADD	X13, X11, X13,LSL #4

0x449e90 B.CC	44a16c

0x449e94 SUB	W1, W6, #1

0x449e98 CMP	W1, W5

0x449e9c B.LT	44a16c

0x449ea0 UDIV	W17, W19, W18

0x449ea4 INDEX	Z3.D, #0, #1

0x449ea8 PTRUE	P0.D, ALL

0x449eac DUP	Z5.D, Z0.D[0]

0x449eb0 DUP	Z6.D, Z1.D[0]

0x449eb4 DUP	Z7.D, Z2.D[0]

0x449eb8 FDUP	Z17.D, #240

0x449ebc FDUP	Z18.D, #112

0x449ec0 MADD	W17, W17, W18, WZR

0x449ec4 DUP	Z16.D, X7

0x449ec8 SXTW	Z16.D, P0/M, Z16.D

0x449ecc SUB	W1, W19, W17

0x449ed0 ORR	W2, WZR, W17

0x449ed4 DUP	Z4.D, X18

0x449ed8 DUP	Z19.D, X5

0x449edc HINT	#0

(1293) 0x449ee0 ADD	Z21.D, Z3.D, Z19.D

(1293) 0x449ee4 MOVPRFX	Z20, Z21

(1293) 0x449ee8 SXTW	Z20.D, P0/M, Z21.D

(1293) 0x449eec CMPGT	P1.D, P0/Z, Z16.D, Z20.D

(1293) 0x449ef0 LD1RD	{Z25.D}, P0/Z, [X0, #1]

(1293) 0x449ef4 LD1RD	{Z26.D}, P0/Z, [X0, #4]

(1293) 0x449ef8 LD1RD	{Z27.D}, P0/Z, [X0, #7]

(1293) 0x449efc LD1RD	{Z28.D}, P0/Z, [X0, #10]

(1293) 0x449f00 ADD	Z3.D, Z3.D, Z4.D

(1293) 0x449f04 LD1RD	{Z29.D}, P0/Z, [X0, #11]

(1293) 0x449f08 LD1RD	{Z30.D}, P0/Z, [X0, #17]

(1293) 0x449f0c SUBS	W2, W2, W18

(1293) 0x449f10 SMOV	X4, V21.S[0]

(1293) 0x449f14 LD1D	{Z23.D}, P0/Z, [X10, X4,LSL #3]

(1293) 0x449f18 LD1D	{Z21.D}, P0/Z, [X8, X4,LSL #3]

(1293) 0x449f1c SEL	Z20.D, P1, Z18.D, Z17.D

(1293) 0x449f20 LD1D	{Z22.D}, P0/Z, [X9, X4,LSL #3]

(1293) 0x449f24 FSUB	Z23.D, Z23.D, Z7.D

(1293) 0x449f28 FSUB	Z21.D, Z21.D, Z5.D

(1293) 0x449f2c FSUB	Z22.D, Z22.D, Z6.D

(1293) 0x449f30 FMUL	Z24.D, Z23.D, Z20.D

(1293) 0x449f34 LD1RD	{Z23.D}, P0/Z, [X0]

(1293) 0x449f38 FMUL	Z21.D, Z21.D, Z20.D

(1293) 0x449f3c FMUL	Z22.D, Z22.D, Z20.D

(1293) 0x449f40 FMUL	Z23.D, Z23.D, Z21.D

(1293) 0x449f44 FMLA	Z23.D, P0/M, Z25.D, Z22.D

(1293) 0x449f48 LD1RD	{Z25.D}, P0/Z, [X0, #2]

(1293) 0x449f4c FMLA	Z23.D, P0/M, Z25.D, Z24.D

(1293) 0x449f50 LD1RD	{Z25.D}, P0/Z, [X0, #3]

(1293) 0x449f54 FRINTM	Z23.D, P0/M, Z23.D

(1293) 0x449f58 FMUL	Z25.D, Z25.D, Z21.D

(1293) 0x449f5c FMLA	Z25.D, P0/M, Z26.D, Z22.D

(1293) 0x449f60 LD1RD	{Z26.D}, P0/Z, [X0, #5]

(1293) 0x449f64 FMLA	Z25.D, P0/M, Z26.D, Z24.D

(1293) 0x449f68 LD1RD	{Z26.D}, P0/Z, [X0, #6]

(1293) 0x449f6c FRINTM	Z25.D, P0/M, Z25.D

(1293) 0x449f70 FMUL	Z26.D, Z26.D, Z21.D

(1293) 0x449f74 FMLA	Z26.D, P0/M, Z27.D, Z22.D

(1293) 0x449f78 LD1RD	{Z27.D}, P0/Z, [X0, #8]

(1293) 0x449f7c FMLA	Z26.D, P0/M, Z27.D, Z24.D

(1293) 0x449f80 LD1RD	{Z27.D}, P0/Z, [X0, #9]

(1293) 0x449f84 FRINTM	Z26.D, P0/M, Z26.D

(1293) 0x449f88 FMUL	Z27.D, Z27.D, Z23.D

(1293) 0x449f8c FMLA	Z27.D, P0/M, Z28.D, Z25.D

(1293) 0x449f90 LD1RD	{Z28.D}, P0/Z, [X0, #12]

(1293) 0x449f94 FMLA	Z27.D, P0/M, Z26.D, Z29.D

(1293) 0x449f98 LD1RD	{Z29.D}, P0/Z, [X0, #14]

(1293) 0x449f9c FMUL	Z28.D, Z28.D, Z23.D

(1293) 0x449fa0 FSUB	Z21.D, Z21.D, Z27.D

(1293) 0x449fa4 LD1RD	{Z27.D}, P0/Z, [X0, #13]

(1293) 0x449fa8 FMAD	Z27.D, P0/M, Z25.D, Z28.D

(1293) 0x449fac LD1RD	{Z28.D}, P0/Z, [X0, #15]

(1293) 0x449fb0 FMLA	Z27.D, P0/M, Z29.D, Z26.D

(1293) 0x449fb4 LD1RD	{Z29.D}, P0/Z, [X0, #16]

(1293) 0x449fb8 FMUL	Z28.D, Z28.D, Z23.D

(1293) 0x449fbc FSUB	Z23.D, Z22.D, Z27.D

(1293) 0x449fc0 MOVPRFX	Z22, Z28

(1293) 0x449fc4 FMLA	Z22.D, P0/M, Z29.D, Z25.D

(1293) 0x449fc8 LD1RD	{Z25.D}, P0/Z, [X0, #19]

(1293) 0x449fcc FMLA	Z22.D, P0/M, Z30.D, Z26.D

(1293) 0x449fd0 LD1RD	{Z26.D}, P0/Z, [X0, #27]

(1293) 0x449fd4 LD1RD	{Z27.D}, P0/Z, [X0, #35]

(1293) 0x449fd8 LD1RD	{Z28.D}, P0/Z, [X0, #40]

(1293) 0x449fdc FSUB	Z22.D, Z24.D, Z22.D

(1293) 0x449fe0 FMUL	Z24.D, Z21.D, Z21.D

(1293) 0x449fe4 FADD	Z25.D, Z25.D, Z21.D

(1293) 0x449fe8 FADD	Z26.D, Z26.D, Z23.D

(1293) 0x449fec FADD	Z27.D, Z27.D, Z22.D

(1293) 0x449ff0 FADD	Z28.D, Z28.D, Z22.D

(1293) 0x449ff4 FMLA	Z24.D, P0/M, Z23.D, Z23.D

(1293) 0x449ff8 FMUL	Z25.D, Z25.D, Z25.D

(1293) 0x449ffc FMLA	Z25.D, P0/M, Z26.D, Z26.D

(1293) 0x44a000 LD1RD	{Z26.D}, P0/Z, [X0, #20]

(1293) 0x44a004 FMLA	Z24.D, P0/M, Z22.D, Z22.D

(1293) 0x44a008 FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a00c LD1RD	{Z27.D}, P0/Z, [X0, #28]

(1293) 0x44a010 FADD	Z26.D, Z26.D, Z21.D

(1293) 0x44a014 FCMGT	P1.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a018 FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a01c FMUL	Z26.D, Z26.D, Z26.D

(1293) 0x44a020 FADD	Z25.D, Z27.D, Z23.D

(1293) 0x44a024 LD1RD	{Z27.D}, P0/Z, [X0, #36]

(1293) 0x44a028 FMAD	Z25.D, P0/M, Z25.D, Z26.D

(1293) 0x44a02c LD1RD	{Z26.D}, P0/Z, [X0, #21]

(1293) 0x44a030 FADD	Z27.D, Z27.D, Z22.D

(1293) 0x44a034 FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a038 FADD	Z26.D, Z26.D, Z21.D

(1293) 0x44a03c LD1RD	{Z27.D}, P0/Z, [X0, #37]

(1293) 0x44a040 FMUL	Z26.D, Z26.D, Z26.D

(1293) 0x44a044 FCMGT	P2.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a048 FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a04c LD1RD	{Z25.D}, P0/Z, [X0, #29]

(1293) 0x44a050 FADD	Z27.D, Z27.D, Z22.D

(1293) 0x44a054 FADD	Z25.D, Z25.D, Z23.D

(1293) 0x44a058 FMAD	Z25.D, P0/M, Z25.D, Z26.D

(1293) 0x44a05c LD1RD	{Z26.D}, P0/Z, [X0, #22]

(1293) 0x44a060 FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a064 LD1RD	{Z27.D}, P0/Z, [X0, #38]

(1293) 0x44a068 FCMGT	P3.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a06c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a070 FADD	Z25.D, Z26.D, Z21.D

(1293) 0x44a074 LD1RD	{Z26.D}, P0/Z, [X0, #30]

(1293) 0x44a078 FMUL	Z25.D, Z25.D, Z25.D

(1293) 0x44a07c FADD	Z27.D, Z27.D, Z22.D

(1293) 0x44a080 FADD	Z26.D, Z26.D, Z23.D

(1293) 0x44a084 FMLA	Z25.D, P0/M, Z26.D, Z26.D

(1293) 0x44a088 LD1RD	{Z26.D}, P0/Z, [X0, #31]

(1293) 0x44a08c FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a090 LD1RD	{Z27.D}, P0/Z, [X0, #39]

(1293) 0x44a094 FADD	Z26.D, Z26.D, Z23.D

(1293) 0x44a098 FCMGT	P4.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a09c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a0a0 LD1RD	{Z25.D}, P0/Z, [X0, #23]

(1293) 0x44a0a4 FADD	Z27.D, Z27.D, Z22.D

(1293) 0x44a0a8 FADD	Z25.D, Z25.D, Z21.D

(1293) 0x44a0ac FMUL	Z25.D, Z25.D, Z25.D

(1293) 0x44a0b0 FMLA	Z25.D, P0/M, Z26.D, Z26.D

(1293) 0x44a0b4 LD1RD	{Z26.D}, P0/Z, [X0, #24]

(1293) 0x44a0b8 FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a0bc LD1RD	{Z27.D}, P0/Z, [X0, #32]

(1293) 0x44a0c0 FADD	Z26.D, Z26.D, Z21.D

(1293) 0x44a0c4 FCMGT	P5.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a0c8 FMUL	Z26.D, Z26.D, Z26.D

(1293) 0x44a0cc FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a0d0 LD1RD	{Z25.D}, P0/Z, [X0, #25]

(1293) 0x44a0d4 FADD	Z27.D, Z27.D, Z23.D

(1293) 0x44a0d8 FMLA	Z26.D, P0/M, Z27.D, Z27.D

(1293) 0x44a0dc LD1RD	{Z27.D}, P0/Z, [X0, #33]

(1293) 0x44a0e0 FADD	Z25.D, Z25.D, Z21.D

(1293) 0x44a0e4 FMLA	Z26.D, P0/M, Z28.D, Z28.D

(1293) 0x44a0e8 LD1RD	{Z28.D}, P0/Z, [X0, #41]

(1293) 0x44a0ec FMUL	Z25.D, Z25.D, Z25.D

(1293) 0x44a0f0 FADD	Z27.D, Z27.D, Z23.D

(1293) 0x44a0f4 FMLA	Z25.D, P0/M, Z27.D, Z27.D

(1293) 0x44a0f8 FCMGT	P6.D, P0/Z, Z24.D, Z26.D

(1293) 0x44a0fc FMINNM	Z24.D, P0/M, Z24.D, Z26.D

(1293) 0x44a100 FADD	Z28.D, Z28.D, Z22.D

(1293) 0x44a104 FMLA	Z25.D, P0/M, Z28.D, Z28.D

(1293) 0x44a108 FCMGT	P7.D, P0/Z, Z24.D, Z25.D

(1293) 0x44a10c FMINNM	Z24.D, P0/M, Z24.D, Z25.D

(1293) 0x44a110 CPY	Z25.D, P1/Z, #1

(1293) 0x44a114 FSQRT	Z24.D, P0/M, Z24.D

(1293) 0x44a118 CPY	Z25.D, P2/M, #2

(1293) 0x44a11c CPY	Z25.D, P3/M, #3

(1293) 0x44a120 CPY	Z25.D, P4/M, #4

(1293) 0x44a124 CPY	Z25.D, P5/M, #5

(1293) 0x44a128 CPY	Z25.D, P6/M, #6

(1293) 0x44a12c CPY	Z25.D, P7/M, #7

(1293) 0x44a130 ST1D	{Z24.D}, P0, [X3, X4,LSL #3]

(1293) 0x44a134 LD1D	{Z24.D}, P0/Z, [X14, Z25.D,LSL #3]

(1293) 0x44a138 FADD	Z21.D, Z24.D, Z21.D

(1293) 0x44a13c FMUL	Z21.D, Z21.D, Z20.D

(1293) 0x44a140 ST1D	{Z21.D}, P0, [X11, X4,LSL #3]

(1293) 0x44a144 LD1D	{Z21.D}, P0/Z, [X15, Z25.D,LSL #3]

(1293) 0x44a148 FADD	Z21.D, Z21.D, Z23.D

(1293) 0x44a14c FMUL	Z21.D, Z21.D, Z20.D

(1293) 0x44a150 ST1D	{Z21.D}, P0, [X12, X4,LSL #3]

(1293) 0x44a154 LD1D	{Z21.D}, P0/Z, [X16, Z25.D,LSL #3]

(1293) 0x44a158 FADD	Z21.D, Z21.D, Z22.D

(1293) 0x44a15c FMUL	Z20.D, Z21.D, Z20.D

(1293) 0x44a160 ST1D	{Z20.D}, P0, [X13, X4,LSL #3]

(1293) 0x44a164 B.NE	449ee0

0x44a168 CBZ	W1, 44a3cc

0x44a16c ADD	W17, W17, W5

0x44a170 FMOV	D3, #-1.0000000

0x44a174 FMOV	D4, #1.0000000

0x44a178 ADD	X18, X0, #304

0x44a17c MOVZ	W1, #2

0x44a180 MOVZ	W2, #3

0x44a184 MOVZ	W4, #4

0x44a188 MOVZ	W5, #5

0x44a18c MOVZ	W19, #6

0x44a190 MOVZ	W20, #7

0x44a194 HINT	#0

0x44a198 HINT	#0

0x44a19c HINT	#0

(1292) 0x44a1a0 LDR	D16, [X10, X17,SXTW #3]

(1292) 0x44a1a4 LDR	D6, [X8, X17,SXTW #3]

(1292) 0x44a1a8 CMP	W17, W7

(1292) 0x44a1ac LDR	D7, [X9, X17,SXTW #3]

(1292) 0x44a1b0 FCSEL	D5, D4, D3, #11

(1292) 0x44a1b4 LDP	Q25, Q24, [X0, #240]

(1292) 0x44a1b8 FSUB	D16, D16, S2

(1292) 0x44a1bc FSUB	D6, D6, S0

(1292) 0x44a1c0 FSUB	D7, D7, S1

(1292) 0x44a1c4 FMUL	D17, D16, D5

(1292) 0x44a1c8 LDP	D16, D18, [X0]

(1292) 0x44a1cc FMUL	D6, D6, D5

(1292) 0x44a1d0 FMUL	D7, D7, D5

(1292) 0x44a1d4 FMUL	D16, D16, D6

(1292) 0x44a1d8 FMADD	D16, D18, D7, D16

(1292) 0x44a1dc LDP	D18, D19, [X0, #16]

(1292) 0x44a1e0 FMADD	D16, D18, D17, D16

(1292) 0x44a1e4 FRINTM	D18, D16

(1292) 0x44a1e8 FMUL	D16, D19, D6

(1292) 0x44a1ec LDP	D19, D20, [X0, #32]

(1292) 0x44a1f0 FMADD	D16, D19, D7, D16

(1292) 0x44a1f4 FMADD	D16, D20, D17, D16

(1292) 0x44a1f8 LDP	D19, D20, [X0, #48]

(1292) 0x44a1fc FMUL	D19, D19, D6

(1292) 0x44a200 FMADD	D19, D20, D7, D19

(1292) 0x44a204 FRINTM	D20, D16

(1292) 0x44a208 LDP	D16, D21, [X0, #64]

(1292) 0x44a20c FMUL	D21, D21, D18

(1292) 0x44a210 FMADD	D16, D16, D17, D19

(1292) 0x44a214 FRINTM	D19, D16

(1292) 0x44a218 LDP	D16, D22, [X0, #80]

(1292) 0x44a21c FMADD	D16, D16, D20, D21

(1292) 0x44a220 FMADD	D16, D19, D22, D16

(1292) 0x44a224 FSUB	D6, D6, S16

(1292) 0x44a228 LDP	D16, D21, [X0, #96]

(1292) 0x44a22c FMUL	D16, D16, D18

(1292) 0x44a230 FMADD	D16, D21, D20, D16

(1292) 0x44a234 LDP	D21, D22, [X0, #112]

(1292) 0x44a238 FMADD	D16, D21, D19, D16

(1292) 0x44a23c FSUB	D16, D7, S16

(1292) 0x44a240 LDP	D21, D23, [X0, #128]

(1292) 0x44a244 FMUL	D7, D22, D18

(1292) 0x44a248 DUP	V26.2D, V16.D[0]

(1292) 0x44a24c FMADD	D7, D21, D20, D7

(1292) 0x44a250 LDP	D20, D21, [X0, #216]

(1292) 0x44a254 FADD	V25.2D, V25.2D, V26.2D

(1292) 0x44a258 FADD	V24.2D, V24.2D, V26.2D

(1292) 0x44a25c FMADD	D7, D23, D19, D7

(1292) 0x44a260 LDP	D18, D19, [X0, #152]

(1292) 0x44a264 LDP	D22, D23, [X0, #280]

(1292) 0x44a268 LDP	Q26, Q27, [X18]

(1292) 0x44a26c FADD	D20, D20, D16

(1292) 0x44a270 FADD	D19, D19, D6

(1292) 0x44a274 FSUB	D7, D17, S7

(1292) 0x44a278 FMUL	D17, D6, D6

(1292) 0x44a27c FADD	D18, D18, D6

(1292) 0x44a280 FMUL	D19, D19, D19

(1292) 0x44a284 FADD	D22, D22, D7

(1292) 0x44a288 DUP	V28.2D, V7.D[0]

(1292) 0x44a28c FMADD	D17, D16, D16, D17

(1292) 0x44a290 FMUL	D18, D18, D18

(1292) 0x44a294 FADD	V26.2D, V26.2D, V28.2D

(1292) 0x44a298 FADD	V27.2D, V27.2D, V28.2D

(1292) 0x44a29c FMADD	D18, D20, D20, D18

(1292) 0x44a2a0 FADD	D20, D21, D16

(1292) 0x44a2a4 FADD	D21, D23, D7

(1292) 0x44a2a8 LDR	D23, [X0, #296]

(1292) 0x44a2ac FMADD	D17, D7, D7, D17

(1292) 0x44a2b0 FMADD	D19, D20, D20, D19

(1292) 0x44a2b4 LDR	D20, [X0, #168]

(1292) 0x44a2b8 FMADD	D18, D22, D22, D18

(1292) 0x44a2bc LDR	D22, [X0, #232]

(1292) 0x44a2c0 FMADD	D19, D21, D21, D19

(1292) 0x44a2c4 FADD	D21, D23, D7

(1292) 0x44a2c8 DUP	V23.2D, V6.D[0]

(1292) 0x44a2cc FADD	D20, D20, D6

(1292) 0x44a2d0 FCMP	D18, D17

(1292) 0x44a2d4 FMUL	D20, D20, D20

(1292) 0x44a2d8 FADD	D22, D22, D16

(1292) 0x44a2dc CSINC	W21, WZR, WZR, #10

(1292) 0x44a2e0 FMADD	D20, D22, D22, D20

(1292) 0x44a2e4 FMADD	D20, D21, D21, D20

(1292) 0x44a2e8 LDP	Q22, Q21, [X0, #176]

(1292) 0x44a2ec FADD	V21.2D, V21.2D, V23.2D

(1292) 0x44a2f0 FADD	V22.2D, V22.2D, V23.2D

(1292) 0x44a2f4 FMUL	V21.2D, V21.2D, V21.2D

(1292) 0x44a2f8 FMINNM	D23, D18, D17

(1292) 0x44a2fc FMUL	V22.2D, V22.2D, V22.2D

(1292) 0x44a300 FMINNM	D28, D19, D23

(1292) 0x44a304 FCMP	D19, D23

(1292) 0x44a308 FMLA	V21.2D, V24.2D, V24.2D

(1292) 0x44a30c CSEL	X21, X1, X21, #11

(1292) 0x44a310 FCMP	D20, D28

(1292) 0x44a314 FMLA	V22.2D, V25.2D, V25.2D

(1292) 0x44a318 FMINNM	D25, D20, D28

(1292) 0x44a31c CSEL	X21, X2, X21, #11

(1292) 0x44a320 FMLA	V21.2D, V27.2D, V27.2D

(1292) 0x44a324 FMLA	V22.2D, V26.2D, V26.2D

(1292) 0x44a328 FMINNM	D24, D22, D25

(1292) 0x44a32c MOV	D17, V22.D[1]

(1292) 0x44a330 FMINNM	D17, D17, D24

(1292) 0x44a334 MOV	V25.D[1], V24.D[0]

(1292) 0x44a338 FMINNM	D18, D21, D17

(1292) 0x44a33c MOV	V17.D[1], V18.D[0]

(1292) 0x44a340 FCMGT	V22.2D, V25.2D, V22.2D

(1292) 0x44a344 FCMGT	V17.2D, V17.2D, V21.2D

(1292) 0x44a348 MOV	D21, V21.D[1]

(1292) 0x44a34c UZP1	V17.4S, V22.4S, V17.4S

(1292) 0x44a350 FMINNM	D18, D21, D18

(1292) 0x44a354 XTN	V17.4H, V17.4S

(1292) 0x44a358 UMOV	W22, V17.H[0]

(1292) 0x44a35c ANDS	WZR, W22, #0

(1292) 0x44a360 UMOV	W22, V17.H[1]

(1292) 0x44a364 CSEL	X21, X4, X21, #1

(1292) 0x44a368 ANDS	WZR, W22, #0

(1292) 0x44a36c UMOV	W22, V17.H[2]

(1292) 0x44a370 CSEL	X21, X5, X21, #1

(1292) 0x44a374 ANDS	WZR, W22, #0

(1292) 0x44a378 UMOV	W22, V17.H[3]

(1292) 0x44a37c FSQRT	D17, D18

(1292) 0x44a380 CSEL	X21, X19, X21, #1

(1292) 0x44a384 ANDS	WZR, W22, #0

(1292) 0x44a388 CSEL	X21, X20, X21, #1

(1292) 0x44a38c LDR	D18, [X14, X21,LSL #3]

(1292) 0x44a390 FADD	D6, D18, D6

(1292) 0x44a394 FMUL	D6, D6, D5

(1292) 0x44a398 STR	D6, [X11, X17,SXTW #3]

(1292) 0x44a39c LDR	D6, [X15, X21,LSL #3]

(1292) 0x44a3a0 STR	D17, [X3, X17,SXTW #3]

(1292) 0x44a3a4 FADD	D6, D6, D16

(1292) 0x44a3a8 FMUL	D6, D6, D5

(1292) 0x44a3ac STR	D6, [X12, X17,SXTW #3]

(1292) 0x44a3b0 LDR	D6, [X16, X21,LSL #3]

(1292) 0x44a3b4 FADD	D6, D6, D7

(1292) 0x44a3b8 FMUL	D5, D6, D5

(1292) 0x44a3bc STR	D5, [X13, X17,SXTW #3]

(1292) 0x44a3c0 ADD	W17, W17, #1

(1292) 0x44a3c4 CMP	W6, W17

(1292) 0x44a3c8 B.NE	44a1a0

0x44a3cc LDP	X20, X19, [SP, #16]

0x44a3d0 LDP	X22, X21, [SP], #32

0x44a3d4 RET

0x44a3d8 HINT	#0

0x44a3dc HINT	#0

Coverage (%)	Name	Source Location	Module
►78.79+	.omp_outlined..62	miniqmc.cpp:482	exec
○	__kmp_invoke_microtask		libomp.so
►15.15+	qmcplusplus::ParticleSet::setA[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:425	exec
○	__kmp_invoke_microtask		libomp.so
►3.03+	.omp_outlined..62	miniqmc.cpp:432	exec
○	__kmp_invoke_microtask		libomp.so
►3.03+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:919	exec
○	.omp_outlined.	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParticleBConds.h:166-219
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:166,185-219

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 5.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.50 to 4.74 cycles (1.58x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.50	7.50	7.50	7.50	3.50	3.50	1.00	1.00	3.33	3.33	3.33	1.00	1.00
cycles	2.50	2.50	7.50	7.50	7.50	7.50	3.50	3.50	1.00	1.00	3.33	3.33	3.33	1.00	1.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	6.63
Overall L1	7.50

Vectorization ratios

INT

all	18%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	26%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	17%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

12% of peak load performance is reached (11.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 449e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X22, X21, [SP, #992]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUBS W19, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 44a3cc <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W17, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X0, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X0, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X0, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W19, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X9, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X8, X10,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X13,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 44a16c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W1, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 44a16c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W17, W19, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
INDEX Z3.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z5.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z6.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z7.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z17.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z18.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD W17, W17, W18, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z16.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
SUB W1, W19, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
CBZ W1, 44a3cc <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W17, W17, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D3, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D4, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X18, X0, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W20, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	ParticleBConds.h:166-219
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:177
/home/hbollore/qaas/qaas-runs/169-816-7419/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds.h:166,185-219

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 5.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.50	7.50	7.50	7.50	3.50	3.50	1.00	1.00	3.33	3.33	3.33	1.00	1.00
cycles	2.50	2.50	7.50	7.50	7.50	7.50	3.50	3.50	1.00	1.00	3.33	3.33	3.33	1.00	1.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	6.63
Overall L1	7.50

Vectorization ratios

INT

all	18%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	26%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	17%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

12% of peak load performance is reached (11.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 449e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X22, X21, [SP, #992]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUBS W19, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 44a3cc <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W17, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X0, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X0, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X0, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W19, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X9, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X8, X10,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X13,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 44a16c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W1, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 44a16c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W17, W19, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
INDEX Z3.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z5.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z6.D, Z1.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z7.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z17.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z18.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD W17, W17, W18, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z16.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
SUB W1, W19, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z4.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
CBZ W1, 44a3cc <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi39EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ELm32ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W17, W17, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D3, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D4, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X18, X0, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W20, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	26.83	0.16
○Loop 1293 - ParticleBConds.h:185-217 - exec	26.83	0.16
○Loop 1292 - ParticleBConds.h:185-217 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code