OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratio(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratio( ...	Module: exec	Source: DiracDeterminantRef.cpp:189-206 [...]	Coverage: 0.17%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 189 - 206

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189: {

190:   UpdateMode             = ORB_PBYP_RATIO;

191:   const int WorkingIndex = iat - FirstIndex;

192:   SPOVTimer->start();

193:   Phi->evaluate(P, iat, psiV);

194:   SPOVTimer->stop();

195:   RatioTimer->start();

196:   // This is an optimization.

197:   // check invRow_id against WorkingIndex to see if getInvRow() has been called

198:   // This is intended to save redundant compuation in TM1 and TM3

199:   if (invRow_id != WorkingIndex)

200:   {

201:     invRow_id = WorkingIndex;

202:     updateEng.getInvRow(psiM, WorkingIndex, invRow);

203:   }

204:   curRatio = simd::dot(invRow.data(), psiV.data(), invRow.size());

205:   RatioTimer->stop();

206:   return curRatio;

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/unique_ptr.h: 173 - 173

--------------------------------------------------------------------------------

173:       pointer    _M_ptr() const { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 178

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178:   inline size_t size() const { return nLocal; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 81 - 82

--------------------------------------------------------------------------------

81:   for (int i = 0; i < n; i++)

82:     res += a[i] * b[i];

0x439fc0 STP	X29, X30, [SP, #976]!

0x439fc4 STP	X22, X21, [SP, #16]

0x439fc8 STP	X20, X19, [SP, #32]

0x439fcc ADD	X29, SP, #0

0x439fd0 ORR	X19, XZR, X0

0x439fd4 STR	WZR, [X0, #12]

0x439fd8 LDR	W8, [X0, #1144]

0x439fdc LDR	X0, [X0, #1120]

0x439fe0 ORR	W21, WZR, W2

0x439fe4 ORR	X22, XZR, X1

0x439fe8 SUB	W20, W2, W8

0x439fec BL	44ed40

0x439ff0 LDR	X0, [X19, #1136]

0x439ff4 ORR	X1, XZR, X22

0x439ff8 ORR	W2, WZR, W21

0x439ffc ADD	X3, X19, #400

0x43a000 LDR	X8, [X0]

0x43a004 LDR	X8, [X8, #16]

0x43a008 BLR	X8

0x43a00c LDR	X0, [X19, #1120]

0x43a010 BL	44ee60

0x43a014 LDR	X0, [X19, #1096]

0x43a018 BL	44ed40

0x43a01c LDR	W8, [X19, #1072]

0x43a020 CMP	W8, W20

0x43a024 B.EQ	43a040

0x43a028 ORR	W2, WZR, W20

0x43a02c ADD	X0, X19, #520

0x43a030 ADD	X1, X19, #208

0x43a034 ADD	X3, X19, #1032

0x43a038 STR	W20, [X19, #1072]

0x43a03c BL	437d30

0x43a040 LDR	X10, [X19, #1040]

0x43a044 CMP	W10, #1

0x43a048 B.LT	43a070

0x43a04c LDR	X8, [X19, #1056]

0x43a050 LDR	X9, [X19, #424]

0x43a054 CNTW	X12, ALL

0x43a058 AND	X10, X10, #6080

0x43a05c CMP	X10, X12

0x43a060 B.CS	43a078

0x43a064 ORR	X11, XZR, XZR

0x43a068 MOVI	D0, #0

0x43a06c B	43a0d0

0x43a070 MOVI	D0, #0

0x43a074 B	43a0f4

0x43a078 UDIV	X11, X10, X12

0x43a07c DUP	Z0.D, #0

0x43a080 ORR	X14, XZR, XZR

0x43a084 ADDVL	X15, X8, #1

0x43a088 ADDVL	X16, X9, #1

0x43a08c PTRUE	P0.D, ALL

0x43a090 ORR	Z1.D, Z0.D, Z0.D

0x43a094 UMSUBL	X13, W11, W12, X10

0x43a098 UMADDL	X11, W11, W12, XZR

0x43a09c HINT	#0

(1058) 0x43a0a0 LD1D	{Z2.D}, P0/Z, [X8, X14,LSL #3]

(1058) 0x43a0a4 LD1D	{Z3.D}, P0/Z, [X15, X14,LSL #3]

(1058) 0x43a0a8 LD1D	{Z4.D}, P0/Z, [X9, X14,LSL #3]

(1058) 0x43a0ac FMLA	Z0.D, P0/M, Z4.D, Z2.D

(1058) 0x43a0b0 LD1D	{Z5.D}, P0/Z, [X16, X14,LSL #3]

(1058) 0x43a0b4 FMLA	Z1.D, P0/M, Z5.D, Z3.D

(1058) 0x43a0b8 ADD	X14, X14, X12

(1058) 0x43a0bc CMP	X11, X14

(1058) 0x43a0c0 B.NE	43a0a0

0x43a0c4 FADD	Z0.D, Z1.D, Z0.D

0x43a0c8 FADDV	D0, P0, Z0.D

0x43a0cc CBZ	X13, 43a0f4

0x43a0d0 SUB	X10, X10, X11

0x43a0d4 UBFM	X11, X11, #61, #60

0x43a0d8 ADD	X9, X9, X11

0x43a0dc ADD	X8, X8, X11

(1059) 0x43a0e0 LDR	D1, [X8], #8

(1059) 0x43a0e4 LDR	D2, [X9], #8

(1059) 0x43a0e8 FMADD	D0, D2, D1, D0

(1059) 0x43a0ec SUBS	X10, X10, #1

(1059) 0x43a0f0 B.NE	43a0e0

0x43a0f4 LDR	X0, [X19, #1096]

0x43a0f8 STR	D0, [X19, #1080]

0x43a0fc BL	44ee60

0x43a100 LDR	D0, [X19, #1080]

0x43a104 LDP	X20, X19, [SP, #32]

0x43a108 LDP	X22, X21, [SP, #16]

0x43a10c LDP	X29, X30, [SP], #48

0x43a110 RET

0x43a114 HINT	#0

0x43a118 HINT	#0

0x43a11c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:485	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:189-206
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:189-206
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:81-82

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 3.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 9.00 to 6.96 cycles (1.29x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 3.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary function is loading 144 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	9.00	9.00	9.00	9.00	2.50	2.50	1.50	1.50	7.33	7.33	7.33	2.50	2.50
cycles	6.50	6.50	9.00	9.00	9.00	9.00	2.50	2.50	1.50	1.50	7.33	7.33	7.33	2.50	2.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	8.75
Overall L1	9.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	6%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 439fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W21, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W20, W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43a040 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 437d30 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43a070 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
AND X10, X10, #6080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 43a078 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 43a0d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 43a0f4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X10, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X16, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UMSUBL X13, W11, W12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UMADDL X11, W11, W12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
FADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
CBZ X13, 43a0f4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X19, #1080]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	DiracDeterminantRef.cpp:189-206
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:189-206
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/unique_ptr.h:173
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:81-82

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 3.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
6% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 3.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary function is loading 144 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	9.00	9.00	9.00	9.00	2.50	2.50	1.50	1.50	7.33	7.33	7.33	2.50	2.50
cycles	6.50	6.50	9.00	9.00	9.00	9.00	2.50	2.50	1.50	1.50	7.33	7.33	7.33	2.50	2.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	8.75
Overall L1	9.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	6%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 439fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W21, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W20, W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W2, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BLR X8	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43a040 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 437d30 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43a070 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
AND X10, X10, #6080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 43a078 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 43a0d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 43a0f4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X10, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X16, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UMSUBL X13, W11, W12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UMADDL X11, W11, W12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
FADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
CBZ X13, 43a0f4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE5ratioERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X19, #1080]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::ratio(qmcplusplus::ParticleSet&, int)–	0.17	0.08
○Loop 1058 - inner_product.hpp:81-82 - exec	0.17	0.08
○Loop 1059 - inner_product.hpp:81-82 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code