OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGrad(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGr ...	Module: exec	Source: DiracDeterminantRef.cpp:83-89 [...]	Coverage: 0.24%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 83 - 89

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83: {

84:   const int WorkingIndex = iat - FirstIndex;

85:   RatioTimer->start();

86:   invRow_id = WorkingIndex;

87:   updateEng.getInvRow(psiM, WorkingIndex, invRow);

88:   GradType g = simd::dot(invRow.data(), dpsiM[WorkingIndex], invRow.size());

89:   RatioTimer->stop();

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

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217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 183

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63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

[...]

183:     return (const_cast<T1&>(a) = b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

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178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 154 - 154

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154:   for (int i = 0; i < n; i++)

0x439a20 STP	X29, X30, [SP, #976]!

0x439a24 STR	X21, [SP, #16]

0x439a28 STP	X20, X19, [SP, #32]

0x439a2c ADD	X29, SP, #0

0x439a30 ORR	X19, XZR, X0

0x439a34 ORR	X20, XZR, X8

0x439a38 LDRSW	X8, [X0, #1144]

0x439a3c LDR	X0, [X0, #1096]

0x439a40 SBFM	X9, X2, #0, #31

0x439a44 SUB	X21, X9, X8

0x439a48 BL	44ed40

0x439a4c ORR	W2, WZR, W21

0x439a50 ADD	X0, X19, #520

0x439a54 ADD	X1, X19, #208

0x439a58 ADD	X3, X19, #1032

0x439a5c STR	W21, [X19, #1072]

0x439a60 BL	437d30

0x439a64 LDR	X11, [X19, #1040]

0x439a68 LDR	X9, [X19, #1056]

0x439a6c LDR	X8, [X19, #320]

0x439a70 CMP	W11, #1

0x439a74 LDR	X10, [X19, #280]

0x439a78 STP	XZR, XZR, [X20, #8]

0x439a7c STR	XZR, [X20]

0x439a80 B.LT	439bac

0x439a84 CNTW	X14, ALL

0x439a88 MADD	X10, X10, X21, XZR

0x439a8c AND	X11, X11, #6080

0x439a90 CMP	X11, X14

0x439a94 B.CS	439aac

0x439a98 ORR	X12, XZR, XZR

0x439a9c MOVI	D0, #0

0x439aa0 MOVI	D2, #0

0x439aa4 MOVI	D1, #0

0x439aa8 B	439b58

0x439aac UDIV	X17, X11, X14

0x439ab0 MOVZ	W12, #24

0x439ab4 DUP	Z0.D, #0

0x439ab8 ORR	X15, XZR, XZR

0x439abc PTRUE	P0.D, ALL

0x439ac0 MADD	X16, X10, X12, X8

0x439ac4 RDVL	X12, #1

0x439ac8 ORR	Z3.D, Z0.D, Z0.D

0x439acc ORR	Z2.D, Z0.D, Z0.D

0x439ad0 ORR	Z4.D, Z0.D, Z0.D

0x439ad4 ORR	Z1.D, Z0.D, Z0.D

0x439ad8 ORR	Z5.D, Z0.D, Z0.D

0x439adc UBFM	X18, X12, #4, #63

0x439ae0 ADD	X0, X18, X18,LSL #1

0x439ae4 UBFM	X18, X0, #59, #58

0x439ae8 UBFM	X0, X0, #60, #59

0x439aec UMSUBL	X13, W17, W14, X11

0x439af0 UMADDL	X12, W17, W14, XZR

0x439af4 ADDVL	X17, X9, #1

0x439af8 HINT	#0

0x439afc HINT	#0

(1050) 0x439b00 ADD	X1, X16, X0

(1050) 0x439b04 LD1D	{Z6.D}, P0/Z, [X9, X15,LSL #3]

(1050) 0x439b08 LD1D	{Z7.D}, P0/Z, [X17, X15,LSL #3]

(1050) 0x439b0c LD3D	{Z16.D, Z17.D, Z18.D}, P0/Z, [X16, MUL VL]

(1050) 0x439b10 ADD	X15, X15, X14

(1050) 0x439b14 ADD	X16, X16, X18

(1050) 0x439b18 LD3D	{Z19.D, Z20.D, Z21.D}, P0/Z, [X1, MUL VL]

(1050) 0x439b1c CMP	X12, X15

(1050) 0x439b20 FMLA	Z1.D, P0/M, Z16.D, Z6.D

(1050) 0x439b24 FMLA	Z2.D, P0/M, Z17.D, Z6.D

(1050) 0x439b28 FMLA	Z0.D, P0/M, Z18.D, Z6.D

(1050) 0x439b2c FMLA	Z5.D, P0/M, Z19.D, Z7.D

(1050) 0x439b30 FMLA	Z4.D, P0/M, Z20.D, Z7.D

(1050) 0x439b34 FMLA	Z3.D, P0/M, Z21.D, Z7.D

(1050) 0x439b38 B.NE	439b00

0x439b3c FADD	Z1.D, Z5.D, Z1.D

0x439b40 FADD	Z2.D, Z4.D, Z2.D

0x439b44 FADD	Z0.D, Z3.D, Z0.D

0x439b48 FADDV	D1, P0, Z1.D

0x439b4c FADDV	D2, P0, Z2.D

0x439b50 FADDV	D0, P0, Z0.D

0x439b54 CBZ	X13, 439ba4

0x439b58 MOVZ	W13, #24

0x439b5c SUB	X11, X11, X12

0x439b60 ADD	X9, X9, X12,LSL #3

0x439b64 MADD	X12, X12, X13, XZR

0x439b68 MADD	X10, X10, X13, X12

0x439b6c ADD	X8, X10, X8

0x439b70 ADD	X8, X8, #8

0x439b74 HINT	#0

0x439b78 HINT	#0

0x439b7c HINT	#0

(1051) 0x439b80 LDP	D4, D5, [X8, #1016]

(1051) 0x439b84 LDR	D6, [X8, #8]

(1051) 0x439b88 LDR	D3, [X9], #8

(1051) 0x439b8c SUBS	X11, X11, #1

(1051) 0x439b90 ADD	X8, X8, #24

(1051) 0x439b94 FMADD	D2, D5, D3, D2

(1051) 0x439b98 FMADD	D1, D4, D3, D1

(1051) 0x439b9c FMADD	D0, D6, D3, D0

(1051) 0x439ba0 B.NE	439b80

0x439ba4 STP	D1, D2, [X20]

0x439ba8 STR	D0, [X20, #16]

0x439bac LDR	X0, [X19, #1096]

0x439bb0 LDP	X20, X19, [SP, #32]

0x439bb4 LDR	X21, [SP, #16]

0x439bb8 LDP	X29, X30, [SP], #48

0x439bbc B	44ee60

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:428	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:83-89
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:83-89
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94,183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.00 to 7.00 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 45% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.00 to 7.24 cycles (1.52x speedup).

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU stores are used in vector version.
46% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
26% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.00 to 1.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary function is loading 92 bytes. The binary function is storing 92 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.00	9.00	11.00	9.00	7.00	7.00	3.00	3.00	6.00	6.00	6.00	3.00	3.00
cycles	3.50	3.50	9.00	9.00	11.00	9.00	7.00	7.00	4.50	4.50	6.00	6.00	6.00	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	9.38
Overall L1	11.00

Vectorization ratios

INT

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	0%
div/sqrt	0%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.00 cycles. At this rate:

8% of peak load performance is reached (8.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 439a20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 437d30 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 439bac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X10, X21, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
AND X11, X11, #6080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 439aac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 439b58 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X11, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MOVZ W12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X16, X10, X12, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z4.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X18, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X18, X18,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X0, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X0, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMSUBL X13, W17, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UMADDL X12, W17, W14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
FADD Z1.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D1, P0, Z1.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
FADDV D2, P0, Z2.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
CBZ X13, 439ba4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X12, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X10, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
STP D1, D2, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D0, [X20, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	DiracDeterminantRef.cpp:83-89
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:83-89
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94,183
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.00 to 7.00 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU stores are used in vector version.
46% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
26% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.00 to 1.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary function is loading 92 bytes. The binary function is storing 92 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	9.00	9.00	11.00	9.00	7.00	7.00	3.00	3.00	6.00	6.00	6.00	3.00	3.00
cycles	3.50	3.50	9.00	9.00	11.00	9.00	7.00	7.00	4.50	4.50	6.00	6.00	6.00	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	9.38
Overall L1	11.00

Vectorization ratios

INT

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	0%
div/sqrt	0%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.00 cycles. At this rate:

8% of peak load performance is reached (8.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 439a20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W21, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 437d30 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 439bac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X10, X21, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
AND X11, X11, #6080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 439aac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 439b58 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X11, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MOVZ W12, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X16, X10, X12, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z4.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X18, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X18, X18,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X0, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X0, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMSUBL X13, W17, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UMADDL X12, W17, W14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X17, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
HINT #0
HINT #0
FADD Z1.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D1, P0, Z1.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
FADDV D2, P0, Z2.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
FADDV D0, P0, Z0.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
CBZ X13, 439ba4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X12, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X10, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
STP D1, D2, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D0, [X20, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)–	0.24	0.12
○Loop 1050 - inner_product.hpp:154-154 - exec	0.24	0.12
○Loop 1051 - inner_product.hpp:154-154 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code