OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate_vgh(qmcplusplus::ParticleSet const&, int)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate_vgh(qmcplusplus::ParticleSet const&, ...	Module: exec	Source: einspline_spo_ref.hpp:202-209 [...]	Coverage: 0.01%

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 191 - 191

--------------------------------------------------------------------------------

191:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h: 213 - 213

--------------------------------------------------------------------------------

213:   inline Type_t operator[](unsigned int i) const { return X[i]; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 202 - 209

--------------------------------------------------------------------------------

202:   {

203:     ScopedTimer local_timer(timer);

204:

205:     auto u = Lattice.toUnit_floor(P.activeR(iat));

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

208:                                         nSplinesPerBlock);

209:   }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 237 - 237

--------------------------------------------------------------------------------

237:   T* data() { return myData; }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline const PosType& activeR(int iat) const { return (activePtcl == iat) ? activePos : R[iat]; }

0x431d60 STR	D10, [SP, #432]!

0x431d64 STP	D9, D8, [SP, #8]

0x431d68 STP	X29, X30, [SP, #24]

0x431d6c STR	X23, [SP, #40]

0x431d70 STP	X22, X21, [SP, #48]

0x431d74 STP	X20, X19, [SP, #64]

0x431d78 ADD	X29, SP, #24

0x431d7c LDR	X19, [X0, #840]

0x431d80 ORR	X20, XZR, X0

0x431d84 ORR	W21, WZR, W2

0x431d88 ORR	X22, XZR, X1

0x431d8c ORR	X0, XZR, X19

0x431d90 BL	44ed40

0x431d94 LDR	X10, [X22, #1512]

0x431d98 LDR	W8, [X22, #2436]

0x431d9c MOVZ	W11, #24

0x431da0 ADD	X9, X22, #2440

0x431da4 LDP	D2, D3, [X20, #208]

0x431da8 SMADDL	X10, W21, W11, X10

0x431dac CMP	W8, W21

0x431db0 LDP	D5, D4, [X20, #224]

0x431db4 LDP	D6, D7, [X20, #256]

0x431db8 CSEL	X8, X9, X10, #0

0x431dbc LDP	D0, D1, [X8]

0x431dc0 FMUL	D2, D2, D0

0x431dc4 FMUL	D3, D3, D0

0x431dc8 FMUL	D0, D5, D0

0x431dcc FMADD	D2, D4, D1, D2

0x431dd0 LDR	D4, [X8, #16]

0x431dd4 MOVZ	X8, #48304

0x431dd8 FMADD	D2, D6, D4, D2

0x431ddc LDP	D6, D16, [X20, #240]

0x431de0 FMADD	D0, D16, D1, D0

0x431de4 FCMP	D2, #0

0x431de8 FMADD	D3, D6, D1, D3

0x431dec LDR	D1, [X20, #272]

0x431df0 FMADD	D3, D7, D4, D3

0x431df4 FMADD	D0, D1, D4, D0

0x431df8 FMOV	D1, X8

0x431dfc FRINTM	D4, D2

0x431e00 LDR	W8, [X20, #48]

0x431e04 FCCMP	D2, D1, #4, #11

0x431e08 FSUB	D2, D2, S4

0x431e0c MOVI	D4, #0

0x431e10 FCSEL	D8, D4, D2, #12

0x431e14 FRINTM	D2, D3

0x431e18 FCMP	D3, #0

0x431e1c FCCMP	D3, D1, #4, #11

0x431e20 FSUB	D2, D3, S2

0x431e24 FCSEL	D9, D4, D2, #12

0x431e28 FCMP	D0, #0

0x431e2c FCCMP	D0, D1, #4, #11

0x431e30 FRINTM	D1, D0

0x431e34 FSUB	D0, D0, S1

0x431e38 FCSEL	D10, D4, D0, #12

0x431e3c CMP	W8, #1

0x431e40 B.LT	431eac

0x431e44 ORR	X21, XZR, XZR

0x431e48 ORR	X22, XZR, XZR

0x431e4c MOVZ	W23, #24

0x431e50 HINT	#0

0x431e54 HINT	#0

0x431e58 HINT	#0

0x431e5c HINT	#0

(941) 0x431e60 LDR	X8, [X20, #744]

(941) 0x431e64 LDRSW	X4, [X20, #64]

(941) 0x431e68 LDR	X0, [X8, X22,LSL #3]

(941) 0x431e6c LDR	X8, [X20, #768]

(941) 0x431e70 LDR	X1, [X8, X21]

(941) 0x431e74 LDR	X8, [X20, #792]

(941) 0x431e78 LDR	X2, [X8, X23]

(941) 0x431e7c LDR	X8, [X20, #816]

(941) 0x431e80 LDR	X3, [X8, X23]

(941) 0x431e84 FMOV	D0, D8

(941) 0x431e88 FMOV	D1, D9

(941) 0x431e8c FMOV	D2, D10

(941) 0x431e90 BL	431f00

(941) 0x431e94 LDRSW	X8, [X20, #48]

(941) 0x431e98 ADD	X22, X22, #1

(941) 0x431e9c ADD	X21, X21, #24

(941) 0x431ea0 ADD	X23, X23, #40

(941) 0x431ea4 CMP	X22, X8

(941) 0x431ea8 B.LT	431e60

0x431eac ORR	X0, XZR, X19

0x431eb0 BL	44ee60

0x431eb4 LDP	D9, D8, [SP, #8]

0x431eb8 LDP	X20, X19, [SP, #64]

0x431ebc LDP	X22, X21, [SP, #48]

0x431ec0 LDR	X23, [SP, #40]

0x431ec4 LDP	X29, X30, [SP, #24]

0x431ec8 LDR	D10, [SP], #80

0x431ecc RET

0x431ed0 BL	409430

0x431ed4 ORR	X20, XZR, X0

0x431ed8 ORR	X0, XZR, X19

0x431edc BL	44ee60

0x431ee0 ORR	X0, XZR, X20

0x431ee4 BL	403dd0

0x431ee8 BL	409430

0x431eec HINT	#0

0x431ef0 HINT	#0

0x431ef4 HINT	#0

0x431ef8 HINT	#0

0x431efc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:217	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	.omp_outlined..62	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	einspline_spo_ref.hpp:202-209
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:191
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:202-209
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:237
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 4.33 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 30% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 9.50 to 2.00 cycles (4.75x speedup).

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.50 to 3.00 cycles (3.17x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 200 bytes. The binary function is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	6.50	6.50	6.50	6.50	7.00	7.00	7.00	7.00	7.67	7.67	7.67	2.00	2.00
cycles	4.00	4.00	6.50	6.50	6.50	6.50	7.00	7.00	7.00	7.00	7.67	7.67	7.67	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Overall L1	9.50

Vectorization ratios

all	35%
load	66%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

21% of peak load performance is reached (21.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 431d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR D10, [SP, #432]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X0, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X22, #1512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X22, #2436]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #2440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D2, D3, [X20, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SMADDL X10, W21, W11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP D5, D4, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D6, D7, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CSEL X8, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D0, D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D2, D4, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D4, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X8, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D2, D6, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D6, D16, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D0, D16, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMADD D3, D6, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D1, [X20, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D3, D7, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D0, D1, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMOV D1, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FRINTM D4, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
LDR W8, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FCCMP D2, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FSUB D2, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D8, D4, D2, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FRINTM D2, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCCMP D3, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FSUB D2, D3, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D9, D4, D2, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCCMP D0, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FRINTM D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D10, D4, D0, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 431eac <_ZN16miniqmcreference17einspline_spo_refIdE12evaluate_vghERKN11qmcplusplus11ParticleSetEi+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D10, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409430 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403dd0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409430 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	einspline_spo_ref.hpp:202-209
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:191
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:202-209
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:237
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 4.33 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.50 to 3.00 cycles (3.17x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 200 bytes. The binary function is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	6.50	6.50	6.50	6.50	7.00	7.00	7.00	7.00	7.67	7.67	7.67	2.00	2.00
cycles	4.00	4.00	6.50	6.50	6.50	6.50	7.00	7.00	7.00	7.00	7.67	7.67	7.67	2.00	2.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Overall L1	9.50

Vectorization ratios

all	35%
load	66%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

21% of peak load performance is reached (21.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 431d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR D10, [SP, #432]!	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X0, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ed40 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X22, #1512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X22, #2436]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, #2440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D2, D3, [X20, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SMADDL X10, W21, W11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP D5, D4, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D6, D7, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CSEL X8, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D0, D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D0, D5, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D2, D4, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D4, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVZ X8, #48304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D2, D6, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDP D6, D16, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D0, D16, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMADD D3, D6, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D1, [X20, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D3, D7, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D0, D1, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMOV D1, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FRINTM D4, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
LDR W8, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FCCMP D2, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FSUB D2, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D8, D4, D2, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FRINTM D2, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCCMP D3, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FSUB D2, D3, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D9, D4, D2, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FCCMP D0, D1, #4, #11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FRINTM D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D10, D4, D0, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 431eac <_ZN16miniqmcreference17einspline_spo_refIdE12evaluate_vghERKN11qmcplusplus11ParticleSetEi+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D10, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409430 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 44ee60 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403dd0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 409430 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate_vgh(qmcplusplus::ParticleSet const&, int)–	0.01	0
○Loop 941 - einspline_spo_ref.hpp:206-208 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code