OV - exec - Function std::vector<double, qmcplusplus::Mallocator<double, 32ul> >::_M_default

	Function: std::vector<double, qmcplusplus::Mallocator<double, 32ul> >::_M_default_append(unsigned lo ...	Module: exec	Source: vector.tcc:613-683 [...]	Coverage: 0.1%

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_uninitialized.h: 687 - 1031

--------------------------------------------------------------------------------

687: 	  for (; __n > 0; --__n, (void) ++__cur)

[...]

1031:       for (; __first != __last; ++__first, (void)++__cur)

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h: 346 - 1762

--------------------------------------------------------------------------------

346: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

353: 	if (__p)

[...]

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1758: 	if (max_size() - size() < __n)

1759: 	  __throw_length_error(__N(__s));

1760:

1761: 	const size_type __len = size() + (std::max)(size(), __n);

1762: 	return (__len < size() || __len > max_size()) ? max_size() : __len;

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 76 - 78

--------------------------------------------------------------------------------

76:     if (n == 0)

77:       throw std::runtime_error("Mallocator::deallocate does not accept size 0 allocations.");

78:     free(p);

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/vector.tcc: 613 - 683

--------------------------------------------------------------------------------

613:     {

614:       if (__n != 0)

615: 	{

616: 	  const size_type __size = size();

617: 	  size_type __navail = size_type(this->_M_impl._M_end_of_storage

618: 					 - this->_M_impl._M_finish);

619:

620: 	  if (__size > max_size() || __navail > max_size() - __size)

621: 	    __builtin_unreachable();

622:

623: 	  if (__navail >= __n)

624: 	    {

625: 	      _GLIBCXX_ASAN_ANNOTATE_GROW(__n);

626: 	      this->_M_impl._M_finish =

[...]

640: 		      std::__uninitialized_default_n_a(__new_start + __size,

[...]

648: 		  _S_relocate(this->_M_impl._M_start, this->_M_impl._M_finish,

[...]

676: 			    this->_M_impl._M_end_of_storage

677: 			    - this->_M_impl._M_start);

678: 	      this->_M_impl._M_start = __new_start;

679: 	      this->_M_impl._M_finish = __new_start + __size + __n;

680: 	      this->_M_impl._M_end_of_storage = __new_start + __len;

681: 	    }

682: 	}

683:     }

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h: 257 - 314

--------------------------------------------------------------------------------

257: 	  ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

[...]

314:       { return __a.allocate(__n); }

0x415f40 STP	X29, X30, [SP, #944]!

0x415f44 STR	X25, [SP, #16]

0x415f48 STP	X24, X23, [SP, #32]

0x415f4c STP	X22, X21, [SP, #48]

0x415f50 STP	X20, X19, [SP, #64]

0x415f54 ADD	X29, SP, #0

0x415f58 CBZ	X1, 416038

0x415f5c LDP	X20, X8, [X0, #8]

0x415f60 ORR	X21, XZR, X1

0x415f64 ORR	X19, XZR, X0

0x415f68 SUB	X8, X8, X20

0x415f6c CMP	X1, X8,ASR #3

0x415f70 B.LS	415fec

0x415f74 LDR	X23, [X19]

0x415f78 SUB	X8, X20, X23

0x415f7c UBFM	X25, X8, #3, #63

0x415f80 EOR	X8, X25, #4155

0x415f84 CMP	X8, X21

0x415f88 B.CC	416154

0x415f8c CMP	X25, X21

0x415f90 CSEL	X8, X25, X21, #8

0x415f94 ADDS	X8, X8, X25

0x415f98 CSINC	W9, WZR, WZR, #3

0x415f9c ANDS	XZR, X8, #4292

0x415fa0 CSINC	W9, W9, WZR, #0

0x415fa4 CMP	W9, #0

0x415fa8 MOVN	X9, #61440

0x415fac CSEL	X22, X9, X8, #1

0x415fb0 CBZ	X22, 416050

0x415fb4 ORR	X0, XZR, X19

0x415fb8 ORR	X1, XZR, X22

0x415fbc BL	40ab10

0x415fc0 LDP	X23, X20, [X19]

0x415fc4 ORR	X24, XZR, X0

0x415fc8 RDVL	X8, #1

0x415fcc ADD	X25, X0, X25,LSL #3

0x415fd0 UBFM	X2, X21, #61, #60

0x415fd4 CMP	X8, #17

0x415fd8 B.CS	416068

0x415fdc ORR	X0, XZR, X25

0x415fe0 ORR	W1, WZR, WZR

0x415fe4 BL	403eb0

0x415fe8 B	416090

0x415fec RDVL	X8, #1

0x415ff0 UBFM	X21, X21, #61, #60

0x415ff4 CMP	X8, #17

0x415ff8 B.CS	416010

0x415ffc ORR	X0, XZR, X20

0x416000 ORR	W1, WZR, WZR

0x416004 ORR	X2, XZR, X21

0x416008 BL	403eb0

0x41600c B	416030

0x416010 WHILELO	P0.B, XZR, X21

0x416014 ORR	X8, XZR, XZR

0x416018 DUP	Z0.B, #0

0x41601c HINT	#0

(309) 0x416020 ST1B	{Z0.B}, P0, [X20, X8]

(309) 0x416024 INCP	X8, P0.B

(309) 0x416028 WHILELO	P0.B, X8, X21

(309) 0x41602c B.MI	416020

0x416030 ADD	X8, X20, X21

0x416034 STR	X8, [X19, #8]

0x416038 LDP	X20, X19, [SP, #64]

0x41603c LDP	X22, X21, [SP, #48]

0x416040 LDP	X24, X23, [SP, #32]

0x416044 LDR	X25, [SP, #16]

0x416048 LDP	X29, X30, [SP], #80

0x41604c RET

0x416050 ORR	X24, XZR, XZR

0x416054 RDVL	X8, #1

0x416058 ADD	X25, XZR, X25,LSL #3

0x41605c UBFM	X2, X21, #61, #60

0x416060 CMP	X8, #17

0x416064 B.CC	415fdc

0x416068 WHILELO	P0.B, XZR, X2

0x41606c ORR	X8, XZR, XZR

0x416070 DUP	Z0.B, #0

0x416074 HINT	#0

0x416078 HINT	#0

0x41607c HINT	#0

(306) 0x416080 ST1B	{Z0.B}, P0, [X25, X8]

(306) 0x416084 INCP	X8, P0.B

(306) 0x416088 WHILELO	P0.B, X8, X2

(306) 0x41608c B.MI	416080

0x416090 CMP	X23, X20

0x416094 B.EQ	416114

0x416098 SUB	X8, X20, X23

0x41609c CNTW	X10, ALL

0x4160a0 SUB	X8, X8, #8

0x4160a4 ORR	X9, XZR, X23

0x4160a8 UBFM	X8, X8, #3, #63

0x4160ac ADD	X11, X8, #1

0x4160b0 ORR	X8, XZR, X24

0x4160b4 CMP	X11, X10

0x4160b8 B.CC	416104

0x4160bc UDIV	X8, X11, X10

0x4160c0 ORR	X12, XZR, XZR

0x4160c4 ADDVL	X14, X23, #1

0x4160c8 ADDVL	X15, X24, #1

0x4160cc PTRUE	P0.D, ALL

0x4160d0 MADD	X13, X8, X10, XZR

0x4160d4 UBFM	X9, X13, #61, #60

0x4160d8 SUB	X11, X11, X13

0x4160dc ADD	X8, X24, X9

0x4160e0 ADD	X9, X23, X9

(308) 0x4160e4 LD1D	{Z0.D}, P0/Z, [X23, X12,LSL #3]

(308) 0x4160e8 LD1D	{Z1.D}, P0/Z, [X14, X12,LSL #3]

(308) 0x4160ec ST1D	{Z0.D}, P0, [X24, X12,LSL #3]

(308) 0x4160f0 ST1D	{Z1.D}, P0, [X15, X12,LSL #3]

(308) 0x4160f4 ADD	X12, X12, X10

(308) 0x4160f8 CMP	X13, X12

(308) 0x4160fc B.NE	4160e4

0x416100 CBZ	X11, 416114

(307) 0x416104 LDR	D0, [X9], #8

(307) 0x416108 STR	D0, [X8], #8

(307) 0x41610c CMP	X9, X20

(307) 0x416110 B.NE	416104

0x416114 CBZ	X23, 41612c

0x416118 LDR	X8, [X19, #16]

0x41611c CMP	X8, X23

0x416120 B.EQ	416160

0x416124 ORR	X0, XZR, X23

0x416128 BL	404190

0x41612c ADD	X8, X25, X21,LSL #3

0x416130 STP	X24, X8, [X19]

0x416134 ADD	X8, X24, X22,LSL #3

0x416138 STR	X8, [X19, #16]

0x41613c LDP	X20, X19, [SP, #64]

0x416140 LDP	X22, X21, [SP, #48]

0x416144 LDP	X24, X23, [SP, #32]

0x416148 LDR	X25, [SP, #16]

0x41614c LDP	X29, X30, [SP], #80

0x416150 RET

0x416154 ADRP	X0,

0x416158 ADD	X0, X0, #568

0x41615c BL	403e90

0x416160 MOVZ	W0, #16

0x416164 BL	404060

0x416168 ORR	X19, XZR, X0

0x41616c ADRP	X1,

0x416170 ADD	X1, X1, #711

0x416174 BL	403c00

0x416178 ADRP	X1,

0x41617c ADRP	X2,

0x416180 ORR	X0, XZR, X19

0x416184 LDR	X1, [X1, #3960]

0x416188 LDR	X2, [X2, #3880]

0x41618c BL	4040d0

0x416190 ORR	X20, XZR, X0

0x416194 ORR	X0, XZR, X19

0x416198 BL	403fe0

0x41619c ORR	X0, XZR, X20

0x4161a0 BL	403dd0

0x4161a4 HINT	#0

0x4161a8 HINT	#0

0x4161ac HINT	#0

0x4161b0 HINT	#0

0x4161b4 HINT	#0

0x4161b8 HINT	#0

0x4161bc HINT	#0

Coverage (%)	Name	Source Location	Module
►90.00+	qmcplusplus::DistanceTableAA<d[...]	DistanceTableAA.h:55	exec
○	qmcplusplus::createDistanceTab[...]	ostream:611	exec
○	qmcplusplus::ParticleSet::addT[...]	vector.tcc:112	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:79	exec
○	.omp_outlined.	miniqmc.cpp:389	exec
○	__kmp_invoke_microtask		libomp.so
►10.00+	qmcplusplus::DistanceTableBA<d[...]	DistanceTableBA.h:51	exec
○	qmcplusplus::createDistanceTab[...]	ostream:611	exec
○	qmcplusplus::ParticleSet::addT[...]	vector.tcc:112	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:79	exec
○	.omp_outlined.	miniqmc.cpp:389	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.tcc:613-683
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_uninitialized.h:687,1031
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:346,353,919,1758-1762
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:76-78
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/vector.tcc:613-626,640,648,676-683
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h:257,314

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.25 to 2.00 cycles (11.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.25 to 14.56 cycles (1.53x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.25 to 5.00 cycles (4.45x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	141
loop length	564
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	22.25	22.25	22.25	22.25	1.00	1.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	13.00	13.00	22.25	22.25	22.25	22.25	1.00	1.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	16.25
Overall L1	22.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.25 cycles. At this rate:

9% of peak load performance is reached (9.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 415f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X1, 416038 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X21, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X8,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.LS 415fec <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X25, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X8, X25, #4155	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 416154 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X25, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS X8, X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W9, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X8, #4292	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W9, W9, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X9, #61440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X22, X9, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X22, 416050 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40ab10 <_ZN11qmcplusplus10MallocatorIdLm32EE8allocateEm>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X20, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X25, X0, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 416068 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403eb0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 416090 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 416010 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403eb0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 416030 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
ADD X8, X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X25, XZR, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415fdc <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
CMP X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 416114 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 416104 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X14, X23, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X15, X24, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X8, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X11, 416114 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X23, 41612c <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 416160 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404190 <@plt_start@+0x790>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X25, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X24, X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X24, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <464154>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e90 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404060 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <46416c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #711	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c00 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X1, <489178>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <48917c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #3880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4040d0 <@plt_start@+0x6d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403fe0 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403dd0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	vector.tcc:613-683
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_uninitialized.h:687,1031
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/stl_vector.h:346,353,919,1758-1762
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:76-78
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/vector.tcc:613-626,640,648,676-683
/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/alloc_traits.h:257,314

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.25 to 5.00 cycles (4.45x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	141
loop length	564
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	22.25	22.25	22.25	22.25	1.00	1.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	13.00	13.00	22.25	22.25	22.25	22.25	1.00	1.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	16.25
Overall L1	22.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.25 cycles. At this rate:

9% of peak load performance is reached (9.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 415f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X1, 416038 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X21, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X8,ASR #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.LS 415fec <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X25, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
EOR X8, X25, #4155	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 416154 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X25, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDS X8, X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W9, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS XZR, X8, #4292	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W9, W9, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X9, #61440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X22, X9, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X22, 416050 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40ab10 <_ZN11qmcplusplus10MallocatorIdLm32EE8allocateEm>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X20, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X25, X0, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 416068 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403eb0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 416090 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 416010 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403eb0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 416030 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
ADD X8, X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X25, XZR, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 415fdc <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
CMP X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 416114 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 416104 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X14, X23, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X15, X24, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X8, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X11, 416114 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X23, 41612c <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 416160 <_ZNSt6vectorIdN11qmcplusplus10MallocatorIdLm32EEEE17_M_default_appendEm+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404190 <@plt_start@+0x790>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X25, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X24, X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X24, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <464154>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403e90 <@plt_start@+0x490>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404060 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <46416c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #711	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403c00 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X1, <489178>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <48917c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #3880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4040d0 <@plt_start@+0x6d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403fe0 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403dd0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼std::vector >::_M_default_append(unsigned long)–	0.1	0.05
○Loop 306 - alloc_traits.h:257-257 - exec	0.1	0.05
○Loop 309 - alloc_traits.h:257-257 - exec	0	0
○Loop 308 - alloc_traits.h:257-257 - exec	0	0
○Loop 307 - stl_uninitialized.h:1031-1031 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code