OV - exec - Loop 90

	Loop Id: 90	Module: exec	Source: NonLocalPP.hpp:131-132 [...]	Coverage: 0.01%

0x40b4e0 LDR	X10, [X28]    [10]

0x40b4e4 UBFM	X11, X24, #61, #60

0x40b4e8 LDUR	X12, [X29, #496]    [14]

0x40b4ec LDR	X14, [SP, #48]    [4]

0x40b4f0 ADD	X9, X9, #1

0x40b4f4 ADD	X12, X12, X8

0x40b4f8 LDR	D0, [X10, X11]    [12]

0x40b4fc LDR	X10, [X22]    [2]

0x40b500 ADD	X14, X14, X8

0x40b504 ADD	X8, X8, #24

0x40b508 LDR	D1, [X12, #16]    [11]

0x40b50c ADD	X10, X10, X11

0x40b510 LDR	X11, [X19]    [8]

0x40b514 LDR	D3, [X10]    [5]

0x40b518 UBFM	X13, X11, #32, #31

0x40b51c SBFM	X11, X11, #60, #31

0x40b520 LDR	D2, [X10, X11]    [1]

0x40b524 LDR	X11, [X20, #64]    [6]

0x40b528 ADD	X13, X10, X13,ASR #29

0x40b52c MADD	X11, X23, X27, X11

0x40b530 LD1	{V3.D[1]}, [X13]    [13]

0x40b534 FMADD	D1, D1, D0, D2

0x40b538 LDR	D2, [X11, #16]    [7]

0x40b53c FADD	D1, D1, D2

0x40b540 LDR	Q2, [X12]    [11]

0x40b544 FMLA	V3.2D, V2.2D, V0.D[0]

0x40b548 LDR	Q0, [X11]    [7]

0x40b54c STR	D1, [X14, #16]    [3]

0x40b550 FADD	V0.2D, V3.2D, V0.2D

0x40b554 STR	Q0, [X14]    [3]

0x40b558 LDR	X10, [X21, #5104]    [9]

0x40b55c LDR	X11, [X21, #5096]    [9]

0x40b560 SUB	X10, X10, X11

0x40b564 UBFM	X10, X10, #3, #63

0x40b568 MADD	W10, W10, W26, WZR

0x40b56c CMP	X9, W10,SXTW

0x40b570 B.LT	40b4e0

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 144 - 145

--------------------------------------------------------------------------------

144:     for (int i = 0; i < D; ++i)

145:       X[i] = base[i * offset];

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h: 988 - 1124

--------------------------------------------------------------------------------

988:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1124: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 131 - 132

--------------------------------------------------------------------------------

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.80
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	3.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	TinyVector.h:144-145,stl_vector.h:988-988,stl_vector.h:1124-1124,VectorSoAContainer.h:231-231,NonLocalPP.hpp:131-132,OperatorTags.h:43-43,OperatorTags.h:63-63,OhmmsVector.h:223-223,OhmmsVector.h:229-229
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.79
Front-end cycles	4.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.46
Vectorization ratio load	25.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	34.62
Vector-efficiency ratio load	31.25
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.80
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	3.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source	TinyVector.h:144-145,stl_vector.h:988-988,stl_vector.h:1124-1124,VectorSoAContainer.h:231-231,NonLocalPP.hpp:131-132,OperatorTags.h:43-43,OperatorTags.h:63-63,OhmmsVector.h:223-223,OhmmsVector.h:229-229
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.79
Front-end cycles	4.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.46
Vectorization ratio load	25.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	34.62
Vector-efficiency ratio load	31.25
Vector-efficiency ratio store	37.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:131-132
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h:988,1124
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:131-132
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 3.33 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 34% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.79 cycles (3.35x speedup).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.50	3.50	3.50	3.50	1.75	1.75	1.75	1.75	6.00	6.00	6.00	0.00	0.00
cycles	0.50	0.50	3.50	3.50	3.50	3.50	1.75	1.75	1.75	1.75	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	27%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b4e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X11, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR X12, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
UBFM X13, X11, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X11, X11, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X10, X13,ASR #29	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X11, X23, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1 {V3.D[1]}, [X13]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
FMADD D1, D1, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D2, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMLA V3.2D, V2.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR Q0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X14, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FADD V0.2D, V3.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR Q0, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X10, [X21, #5104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X21, #5096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W10, W10, W26, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP X9, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.LT 40b4e0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::NonLocalPP::evaluate(qmcplusplus::ParticleSet const&, qmcplusplus::WaveFunction&)
Source file and lines	NonLocalPP.hpp:131-132
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h:988,1124
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:131-132
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 3.33 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.50	3.50	3.50	3.50	1.75	1.75	1.75	1.75	6.00	6.00	6.00	0.00	0.00
cycles	0.50	0.50	3.50	3.50	3.50	3.50	1.75	1.75	1.75	1.75	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	27%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b4e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X11, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR X12, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
UBFM X13, X11, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X11, X11, #60, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X13, X10, X13,ASR #29	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X11, X23, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LD1 {V3.D[1]}, [X13]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
FMADD D1, D1, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D2, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMLA V3.2D, V2.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR Q0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X14, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FADD V0.2D, V3.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR Q0, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X10, [X21, #5104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X21, #5096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W10, W10, W26, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP X9, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
B.LT 40b4e0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code