OV - exec - Loop 2735

	Loop Id: 2735	Module: exec	Source: ParticleBConds3DSoa.h:280-298 [...]	Coverage: 4.14%

0x4a2d60 SUB	X12, X29, #64

0x4a2d64 LD1D	{Z12.D}, P0/Z, [X25, X4,LSL #3]    [11]

0x4a2d68 ORR	Z27.D, Z15.D, Z15.D

0x4a2d6c LDR	Z7, [X12, #507, MUL VL]    [7]

0x4a2d70 SUB	X12, X29, #64

0x4a2d74 LD1D	{Z13.D}, P0/Z, [X9, X4,LSL #3]    [4]

0x4a2d78 FSUB	Z12.D, Z12.D, Z7.D

0x4a2d7c LDR	Z7, [X12, #506, MUL VL]    [2]

0x4a2d80 SUB	X12, X29, #64

0x4a2d84 LD1D	{Z14.D}, P0/Z, [X16, X4,LSL #3]    [6]

0x4a2d88 FMUL	Z15.D, Z15.D, Z12.D

0x4a2d8c FMUL	Z26.D, Z0.D, Z12.D

0x4a2d90 FMUL	Z12.D, Z3.D, Z12.D

0x4a2d94 FSUB	Z13.D, Z13.D, Z7.D

0x4a2d98 LDR	Z7, [X12, #505, MUL VL]    [3]

0x4a2d9c SUB	X12, X29, #64

0x4a2da0 FMLA	Z15.D, P0/M, Z28.D, Z13.D

0x4a2da4 FMLA	Z26.D, P0/M, Z1.D, Z13.D

0x4a2da8 FMLA	Z12.D, P0/M, Z4.D, Z13.D

0x4a2dac FSUB	Z14.D, Z14.D, Z7.D

0x4a2db0 LDR	Z7, [X12, #508, MUL VL]    [14]

0x4a2db4 SUB	X12, X29, #64

0x4a2db8 FMLA	Z15.D, P0/M, Z29.D, Z14.D

0x4a2dbc FMLA	Z26.D, P0/M, Z2.D, Z14.D

0x4a2dc0 FMLA	Z12.D, P0/M, Z5.D, Z14.D

0x4a2dc4 MOVPRFX	Z13, Z15

0x4a2dc8 FRINTA	Z13.D, P0/M, Z15.D

0x4a2dcc MOVPRFX	Z14, Z26

0x4a2dd0 FRINTA	Z14.D, P0/M, Z26.D

0x4a2dd4 FSUB	Z13.D, Z15.D, Z13.D

0x4a2dd8 FSUB	Z26.D, Z26.D, Z14.D

0x4a2ddc MOVPRFX	Z14, Z12

0x4a2de0 FRINTA	Z14.D, P0/M, Z12.D

0x4a2de4 FSUB	Z12.D, Z12.D, Z14.D

0x4a2de8 FMUL	Z14.D, Z6.D, Z13.D

0x4a2dec FMLA	Z14.D, P0/M, Z7.D, Z26.D

0x4a2df0 LDR	Z7, [X12, #511, MUL VL]    [13]

0x4a2df4 SUB	X12, X29, #64

0x4a2df8 FMLA	Z14.D, P0/M, Z12.D, Z7.D

0x4a2dfc ST1D	{Z14.D}, P0, [X6, X4,LSL #3]    [1]

0x4a2e00 LDR	Z15, [X12, #510, MUL VL]    [12]

0x4a2e04 SUB	X12, X29, #64

0x4a2e08 LDR	Z7, [X12, #509, MUL VL]    [10]

0x4a2e0c FMUL	Z15.D, Z15.D, Z13.D

0x4a2e10 FMUL	Z13.D, Z10.D, Z13.D

0x4a2e14 FMLA	Z15.D, P0/M, Z7.D, Z26.D

0x4a2e18 FMAD	Z26.D, P0/M, Z11.D, Z13.D

0x4a2e1c FMLA	Z26.D, P0/M, Z22.D, Z12.D

0x4a2e20 FMLA	Z15.D, P0/M, Z9.D, Z12.D

0x4a2e24 FMUL	Z12.D, Z14.D, Z14.D

0x4a2e28 ST1D	{Z26.D}, P0, [X1, X4,LSL #3]    [9]

0x4a2e2c FMAD	Z26.D, P0/M, Z26.D, Z12.D

0x4a2e30 ST1D	{Z15.D}, P0, [X8, X4,LSL #3]    [5]

0x4a2e34 FMLA	Z26.D, P0/M, Z15.D, Z15.D

0x4a2e38 ORR	Z15.D, Z27.D, Z27.D

0x4a2e3c FSQRT	Z26.D, P0/M, Z26.D

0x4a2e40 ST1D	{Z26.D}, P0, [X15, X4,LSL #3]    [8]

0x4a2e44 ADD	X4, X4, X24

0x4a2e48 CMP	X26, X4

0x4a2e4c B.NE	4a2d60

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 228 - 228

--------------------------------------------------------------------------------

228:           for (int iel = first; iel < last; iel++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	18.00
Front-end cycles	7.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	18.00
P6 cycles	18.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.33
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.89
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.50
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	18.00
Front-end cycles	7.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	18.00
P6 cycles	18.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.33
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.89
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.50
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 320 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	18.00	18.00	2.00	2.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	18.00	18.00	13.50	13.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.50
Data deps.	4.00
Overall L1	18.00

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

18% of peak load performance is reached (17.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a2d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z12.D}, P0/Z, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ORR Z27.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z13.D}, P0/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z12.D, Z12.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z14.D}, P0/Z, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z12.D, Z3.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z13.D, Z13.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z15.D, P0/M, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z14.D, Z14.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z15.D, P0/M, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z2.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P0/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z13, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z13.D, P0/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z14, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z14.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z13.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z14.D, P0/M, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z12.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z14.D, Z6.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z14.D, P0/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z7, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z14.D, P0/M, Z12.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z14.D}, P0, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z15, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z7, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z13.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z15.D, P0/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z26.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z15.D, P0/M, Z9.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z12.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z26.D}, P0, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMAD Z26.D, P0/M, Z26.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z15.D}, P0, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMLA Z26.D, P0/M, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z15.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z26.D}, P0, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X26, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 4a2d60 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 320 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	18.00	18.00	2.00	2.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	18.00	18.00	13.50	13.50	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.50
Data deps.	4.00
Overall L1	18.00

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

18% of peak load performance is reached (17.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a2d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z12.D}, P0/Z, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ORR Z27.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z13.D}, P0/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z12.D, Z12.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z14.D}, P0/Z, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z15.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z12.D, Z3.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z13.D, Z13.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z15.D, P0/M, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z14.D, Z14.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z7, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z15.D, P0/M, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z2.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z12.D, P0/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z13, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z13.D, P0/M, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z14, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z14.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z13.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z26.D, Z26.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z14.D, P0/M, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z12.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z14.D, Z6.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z14.D, P0/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z7, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMLA Z14.D, P0/M, Z12.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z14.D}, P0, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LDR Z15, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR Z7, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z15.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z13.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z15.D, P0/M, Z7.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z26.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z26.D, P0/M, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z15.D, P0/M, Z9.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z12.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z26.D}, P0, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMAD Z26.D, P0/M, Z26.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z15.D}, P0, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMLA Z26.D, P0/M, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ORR Z15.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z26.D}, P0, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X26, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 4a2d60 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code