OV - exec - Loop 1551

	Loop Id: 1551	Module: exec	Source: ParticleBConds3DSoa.h:234-255	Coverage: 1.44%

0x455a2c ADD	W18, W5, W16

0x455a30 LD1RD	{Z17.D}, P0/Z, [X0, #9]    [5]

0x455a34 LD1RD	{Z18.D}, P0/Z, [X0, #10]    [5]

0x455a38 LD1RD	{Z19.D}, P0/Z, [X0, #12]    [5]

0x455a3c ADD	W16, W16, W14

0x455a40 SBFM	X18, X18, #0, #31

0x455a44 CMP	W15, W16

0x455a48 LD1D	{Z6.D}, P0/Z, [X8, X18,LSL #3]    [4]

0x455a4c LD1D	{Z7.D}, P0/Z, [X9, X18,LSL #3]    [3]

0x455a50 LD1D	{Z16.D}, P0/Z, [X10, X18,LSL #3]    [2]

0x455a54 FSUB	Z6.D, Z6.D, Z3.D

0x455a58 FSUB	Z7.D, Z7.D, Z4.D

0x455a5c FSUB	Z16.D, Z16.D, Z5.D

0x455a60 FMUL	Z17.D, Z17.D, Z6.D

0x455a64 FMUL	Z19.D, Z19.D, Z6.D

0x455a68 FMLA	Z17.D, P0/M, Z18.D, Z7.D

0x455a6c LD1RD	{Z18.D}, P0/Z, [X0, #11]    [5]

0x455a70 FMLA	Z17.D, P0/M, Z18.D, Z16.D

0x455a74 LD1RD	{Z18.D}, P0/Z, [X0, #13]    [5]

0x455a78 FMAD	Z18.D, P0/M, Z7.D, Z19.D

0x455a7c LD1RD	{Z19.D}, P0/Z, [X0, #14]    [5]

0x455a80 FMLA	Z18.D, P0/M, Z19.D, Z16.D

0x455a84 LD1RD	{Z19.D}, P0/Z, [X0, #15]    [5]

0x455a88 FMUL	Z6.D, Z19.D, Z6.D

0x455a8c LD1RD	{Z19.D}, P0/Z, [X0, #16]    [5]

0x455a90 FMLA	Z6.D, P0/M, Z19.D, Z7.D

0x455a94 LD1RD	{Z7.D}, P0/Z, [X0, #17]    [5]

0x455a98 FMLA	Z6.D, P0/M, Z7.D, Z16.D

0x455a9c MOVPRFX	Z7, Z17

0x455aa0 FRINTA	Z7.D, P0/M, Z17.D

0x455aa4 FSUB	Z7.D, Z17.D, Z7.D

0x455aa8 MOVPRFX	Z17, Z6

0x455aac FRINTA	Z17.D, P0/M, Z6.D

0x455ab0 MOVPRFX	Z16, Z18

0x455ab4 FRINTA	Z16.D, P0/M, Z18.D

0x455ab8 FSUB	Z16.D, Z18.D, Z16.D

0x455abc LD1RD	{Z18.D}, P0/Z, [X0, #1]    [5]

0x455ac0 FSUB	Z6.D, Z6.D, Z17.D

0x455ac4 LD1RD	{Z17.D}, P0/Z, [X0]    [5]

0x455ac8 FMUL	Z17.D, Z17.D, Z7.D

0x455acc FMLA	Z17.D, P0/M, Z18.D, Z16.D

0x455ad0 LD1RD	{Z18.D}, P0/Z, [X0, #2]    [5]

0x455ad4 FMLA	Z17.D, P0/M, Z6.D, Z18.D

0x455ad8 ST1D	{Z17.D}, P0, [X11, X18,LSL #3]    [6]

0x455adc LD1RD	{Z17.D}, P0/Z, [X0, #3]    [5]

0x455ae0 LD1RD	{Z18.D}, P0/Z, [X0, #4]    [5]

0x455ae4 FMUL	Z17.D, Z17.D, Z7.D

0x455ae8 FMLA	Z17.D, P0/M, Z18.D, Z16.D

0x455aec LD1RD	{Z18.D}, P0/Z, [X0, #5]    [5]

0x455af0 FMLA	Z17.D, P0/M, Z18.D, Z6.D

0x455af4 ST1D	{Z17.D}, P0, [X12, X18,LSL #3]    [1]

0x455af8 LD1RD	{Z17.D}, P0/Z, [X0, #6]    [5]

0x455afc FMUL	Z7.D, Z17.D, Z7.D

0x455b00 LD1RD	{Z17.D}, P0/Z, [X0, #7]    [5]

0x455b04 FMLA	Z7.D, P0/M, Z17.D, Z16.D

0x455b08 LD1RD	{Z16.D}, P0/Z, [X0, #8]    [5]

0x455b0c FMAD	Z6.D, P0/M, Z16.D, Z7.D

0x455b10 ST1D	{Z6.D}, P0, [X13, X18,LSL #3]    [7]

0x455b14 LD1D	{Z7.D}, P0/Z, [X11, X18,LSL #3]    [6]

0x455b18 LD1D	{Z16.D}, P0/Z, [X12, X18,LSL #3]    [1]

0x455b1c FMUL	Z7.D, Z7.D, Z7.D

0x455b20 FMAD	Z6.D, P0/M, Z6.D, Z7.D

0x455b24 FMLA	Z6.D, P0/M, Z16.D, Z16.D

0x455b28 FSQRT	Z6.D, P0/M, Z6.D

0x455b2c ST1D	{Z6.D}, P0, [X3, X18,LSL #3]    [8]

0x455b30 B.NE	455a2c

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 255

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	17.00
P6 cycles	17.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.41
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	63.49
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	85.71
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	75.79
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	17.00
Front-end cycles	8.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	17.00
P6 cycles	17.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.88
Nb FLOP add-sub	24.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.41
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	63.49
Vectorization ratio load	21.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	85.71
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	75.79
Vector-efficiency ratio load	41.30
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-255.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
85% of VPU addition or subtraction instructions are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	28%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	63%
load	21%
store	100%
mul	100%
add-sub	85%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

18% of peak load performance is reached (17.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 455a2c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD W18, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1RD {Z17.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z19.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD W16, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SBFM X18, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LD1D {Z6.D}, P0/Z, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z6.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z7.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z17.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z18.D, P0/M, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z19.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z19.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z19.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z6.D, P0/M, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z7.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z6.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z7.D, P0/M, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z7.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z17, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z17.D, P0/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z16, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z16.D, P0/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z16.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z18.D}, P0/Z, [X0, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z6.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z17.D}, P0/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P0, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z17.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z7.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z16.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z6.D, P0/M, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z6.D}, P0, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z7.D}, P0/Z, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z6.D, P0/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z6.D, P0/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z6.D}, P0, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 455a2c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
85% of VPU addition or subtraction instructions are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

80: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	2.00	2.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	17.00	17.00	13.50	13.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.25
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	28%
load	21%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	63%
load	21%
store	100%
mul	100%
add-sub	85%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

18% of peak load performance is reached (17.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 455a2c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD W18, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1RD {Z17.D}, P0/Z, [X0, #9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z19.D}, P0/Z, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD W16, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SBFM X18, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LD1D {Z6.D}, P0/Z, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z6.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z7.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z17.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z18.D, P0/M, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z19.D}, P0/Z, [X0, #14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z19.D}, P0/Z, [X0, #15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z19.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z19.D}, P0/Z, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z6.D, P0/M, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z7.D}, P0/Z, [X0, #17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z6.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z7.D, P0/M, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z7.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z17, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z17.D, P0/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
MOVPRFX Z16, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FRINTA Z16.D, P0/M, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1
FSUB Z16.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z18.D}, P0/Z, [X0, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z6.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z17.D}, P0/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X0, #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z18.D}, P0/Z, [X0, #4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z17.D, P0/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z18.D}, P0/Z, [X0, #5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z17.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z17.D}, P0, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X0, #6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z17.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z17.D}, P0/Z, [X0, #7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z7.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1RD {Z16.D}, P0/Z, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z6.D, P0/M, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z6.D}, P0, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z7.D}, P0/Z, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z6.D, P0/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z6.D, P0/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08
ST1D {Z6.D}, P0, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 455a2c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code