| Loop Id: 1086 | Module: exec | Source: inner_product.hpp:155-155 [...] | Coverage: 0.33% |
|---|
| Loop Id: 1086 | Module: exec | Source: inner_product.hpp:155-155 [...] | Coverage: 0.33% |
|---|
0x43a640 ADD X1, X16, X0 |
0x43a644 LD1D {Z6.D}, P0/Z, [X10, X15,LSL #3] [1] |
0x43a648 LD1D {Z7.D}, P0/Z, [X17, X15,LSL #3] [4] |
0x43a64c LD3D {Z16.D, Z17.D, Z18.D}, P0/Z, [X16, MUL VL] [3] |
0x43a650 ADD X15, X15, X14 |
0x43a654 ADD X16, X16, X18 |
0x43a658 LD3D {Z19.D, Z20.D, Z21.D}, P0/Z, [X1, MUL VL] [2] |
0x43a65c CMP X12, X15 |
0x43a660 FMLA Z0.D, P0/M, Z16.D, Z6.D |
0x43a664 FMLA Z2.D, P0/M, Z17.D, Z6.D |
0x43a668 FMLA Z4.D, P0/M, Z18.D, Z6.D |
0x43a66c FMLA Z1.D, P0/M, Z19.D, Z7.D |
0x43a670 FMLA Z3.D, P0/M, Z20.D, Z7.D |
0x43a674 FMLA Z5.D, P0/M, Z21.D, Z7.D |
0x43a678 B.NE 43a640 |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 94 - 94 |
-------------------------------------------------------------------------------- |
94: (const_cast<T1&>(a) += b); |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155 |
-------------------------------------------------------------------------------- |
155: for (int i = 0; i < n; i++) |
| Coverage (%) | Name | Source Location | Module |
|---|
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.23 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P6, P7, |
| Function | miniqmcreference::DiracDeterminantRef |
| Source | OperatorTags.h:94-94,inner_product.hpp:155-155 |
| Source loop unroll info | unrolled by 2 |
| Source loop unroll confidence level | low |
| Unroll/vectorization loop type | NA |
| Unroll factor | 2 |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 4.00 |
| CQA cycles if fully vectorized | 3.25 |
| Front-end cycles | 1.88 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 4.00 |
| P6 cycles | 4.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 2.00 |
| P10 cycles | 2.00 |
| P11 cycles | 0.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 15.00 |
| Nb uops | 15.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 12.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 24.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 80.00 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 85.00 |
| Vector-efficiency ratio load | 62.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.23 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P6, P7, |
| Function | miniqmcreference::DiracDeterminantRef |
| Source | OperatorTags.h:94-94,inner_product.hpp:155-155 |
| Source loop unroll info | unrolled by 2 |
| Source loop unroll confidence level | low |
| Unroll/vectorization loop type | NA |
| Unroll factor | 2 |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 4.00 |
| CQA cycles if fully vectorized | 3.25 |
| Front-end cycles | 1.88 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 4.00 |
| P6 cycles | 4.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 2.00 |
| P10 cycles | 2.00 |
| P11 cycles | 0.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 15.00 |
| Nb uops | 15.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 12.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 24.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 80.00 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 85.00 |
| Vector-efficiency ratio load | 62.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | miniqmcreference::DiracDeterminantRef |
| Source file and lines | inner_product.hpp:155-155 |
| Module | exec |
| nb instructions | 15 |
| loop length | 60 |
| nb stack references | 0 |
| front end | 1.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 | 4.00 | 0.00 | 0.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 | 4.00 | 3.00 | 3.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 1.88 |
| Data deps. | 2.00 |
| Overall L1 | 4.00 |
| all | 50% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 80% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X1, X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LD1D {Z6.D}, P0/Z, [X10, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z7.D}, P0/Z, [X17, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD3D {Z16.D, Z17.D, Z18.D}, P0/Z, [X16, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 11 | 3.00 |
| ADD X15, X15, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X16, X16, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LD3D {Z19.D, Z20.D, Z21.D}, P0/Z, [X1, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 11 | 3.00 |
| CMP X12, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| FMLA Z0.D, P0/M, Z16.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z2.D, P0/M, Z17.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z4.D, P0/M, Z18.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z1.D, P0/M, Z19.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z3.D, P0/M, Z20.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z5.D, P0/M, Z21.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| B.NE 43a640 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xe0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | miniqmcreference::DiracDeterminantRef |
| Source file and lines | inner_product.hpp:155-155 |
| Module | exec |
| nb instructions | 15 |
| loop length | 60 |
| nb stack references | 0 |
| front end | 1.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 | 4.00 | 0.00 | 0.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 | 4.00 | 3.00 | 3.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 1.88 |
| Data deps. | 2.00 |
| Overall L1 | 4.00 |
| all | 50% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 80% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X1, X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LD1D {Z6.D}, P0/Z, [X10, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z7.D}, P0/Z, [X17, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD3D {Z16.D, Z17.D, Z18.D}, P0/Z, [X16, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 11 | 3.00 |
| ADD X15, X15, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X16, X16, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LD3D {Z19.D, Z20.D, Z21.D}, P0/Z, [X1, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 11 | 3.00 |
| CMP X12, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| FMLA Z0.D, P0/M, Z16.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z2.D, P0/M, Z17.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z4.D, P0/M, Z18.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z1.D, P0/M, Z19.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z3.D, P0/M, Z20.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMLA Z5.D, P0/M, Z21.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| B.NE 43a640 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xe0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |