OV - exec - Function qmcplusplus::ParticleSet::makeMove(int, qmcplusplus::TinyVector<double, 3u> const&, bool)

	Function: qmcplusplus::ParticleSet::makeMove(int, qmcplusplus::TinyVector<double, 3u> const&, bool)	Module: exec	Source: OhmmsVector.h:223-223 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 43

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43:     return (a + b);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

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223:     return X[i];

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp: 265 - 268

--------------------------------------------------------------------------------

265:   active_ptcl_     = iat;

266:   active_pos_      = R[iat] + displ;

267:   active_spin_val_ = spins[iat];

268:   computeNewPosDistTables(iat, active_pos_, maybe_accept);

0x44a420 LDR	X8, [X0, #64]

0x44a424 MOVZ	W9, #24

0x44a428 LDR	D1, [X2, #16]

0x44a42c LDR	Q2, [X2]

0x44a430 SMADDL	X9, W1, W9, X8

0x44a434 ADD	X8, X0, #296

0x44a438 STR	W1, [X0, #292]

0x44a43c ORR	X2, XZR, X8

0x44a440 LDR	D0, [X9, #16]

0x44a444 FADD	D0, D1, D0

0x44a448 LDR	Q1, [X9]

0x44a44c LDR	X9, [X0, #104]

0x44a450 STR	D0, [X0, #312]

0x44a454 FADD	V1.2D, V2.2D, V1.2D

0x44a458 STR	Q1, [X8]

0x44a45c LDR	D0, [X9, X1,SXTW #3]

0x44a460 STR	D0, [X0, #320]

0x44a464 B	44a470

0x44a468 HINT	#0

0x44a46c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:223-223
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:265-268

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.67 to 2.83 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 36% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.67 to 1.21 cycles (3.03x speedup).

Details

44% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 72 bytes. The binary function is storing 36 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	1.50	1.50	1.00	1.00	3.67	3.67	3.67	0.50	0.50
cycles	0.50	0.50	1.00	1.00	1.00	1.00	1.50	1.50	1.00	1.00	3.67	3.67	3.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.25
Overall L1	3.67

Vectorization ratios

INT

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.67 cycles. At this rate:

20% of peak load performance is reached (19.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44a420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X8, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR Q2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SMADDL X9, W1, W9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [X0, #292]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR Q1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X9, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X0, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
FADD V1.2D, V2.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR Q1, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X9, X1,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D0, [X0, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 44a470 <_ZN11qmcplusplus11ParticleSet23computeNewPosDistTablesEiRKNS_10TinyVectorIdLj3EEEb>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	OhmmsVector.h:223-223
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:265-268

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.67 to 2.83 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 72 bytes. The binary function is storing 36 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	1.50	1.50	1.00	1.00	3.67	3.67	3.67	0.50	0.50
cycles	0.50	0.50	1.00	1.00	1.00	1.00	1.50	1.50	1.00	1.00	3.67	3.67	3.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.25
Overall L1	3.67

Vectorization ratios

INT

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.67 cycles. At this rate:

20% of peak load performance is reached (19.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44a420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X8, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR Q2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SMADDL X9, W1, W9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [X0, #292]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR Q1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X9, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X0, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
FADD V1.2D, V2.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR Q1, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X9, X1,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D0, [X0, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 44a470 <_ZN11qmcplusplus11ParticleSet23computeNewPosDistTablesEiRKNS_10TinyVectorIdLj3EEEb>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
○qmcplusplus::ParticleSet::makeMove(int, qmcplusplus::TinyVector const&, bool)	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code