OV - exec - Loop 949

0x431180 ADD	X21, X21, #24

0x431184 CMP	X22, W8,SXTW

0x431188 B.GE	4311d4

0x43118c LDR	W10, [X20, #64]    [2]

0x431190 LDR	W11, [X20, #8]    [2]

0x431194 MADD	W9, W8, W22, WZR

0x431198 ADD	X22, X22, #1

0x43119c MADD	W10, W10, W22, WZR

0x4311a0 CMP	W11, W10

0x4311a4 CSEL	W10, W11, W10, #11

0x4311a8 SUB	W10, W10, W9

0x4311ac CMP	W10, #1

0x4311b0 B.LT	431180

0x4311b4 LDR	X8, [X19, #24]    [3]

0x4311b8 UBFM	X2, X10, #61, #31

0x4311bc ADD	X0, X8, W9,SXTW #3

0x4311c0 LDR	X8, [X20, #784]    [2]

0x4311c4 LDR	X1, [X8, X21]    [1]

0x4311c8 BL	404cd0

0x4311cc LDR	W8, [X20, #48]    [2]

0x4311d0 B	431180

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algobase.h: 235 - 431

--------------------------------------------------------------------------------

235:       if (__b < __a)

[...]

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 183 - 187

--------------------------------------------------------------------------------

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h: 1124 - 1256

--------------------------------------------------------------------------------

1124: 	return *(this->_M_impl._M_start + __n);

[...]

1256:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algo.h: 754 - 754

--------------------------------------------------------------------------------

754:       if (__n2 <= 0)

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 248 - 248

--------------------------------------------------------------------------------

248:   inline pointer data() { return X; }

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	stl_algobase.h:235-235,stl_algobase.h:429-431,einspline_spo_ref.hpp:183-187,stl_vector.h:1124-1124,stl_vector.h:1256-1256,stl_algo.h:754-754,OhmmsVector.h:248-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.44
Front-end cycles	2.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P2, P3, P4, P5,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	stl_algobase.h:235-235,stl_algobase.h:429-431,einspline_spo_ref.hpp:183-187,stl_vector.h:1124-1124,stl_vector.h:1256-1256,stl_algo.h:754-754,OhmmsVector.h:248-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.44
Front-end cycles	2.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algobase.h:235,429-431
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h:1124,1256
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algo.h:754
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.44 cycles (6.86x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 0.50 cycles (6.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X22, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
B.GE 4311d4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W10, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W11, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W9, W8, W22, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD W10, W10, W22, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W10, W11, W10, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W10, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 431180 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X2, X10, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X8, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [X20, #784]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X8, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 404cd0 <@plt_start@+0x6e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W8, [X20, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 431180 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	einspline_spo_ref.hpp:183-187
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algobase.h:235,429-431
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h:1124,1256
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algo.h:754
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.44 cycles (6.86x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 0.50 cycles (6.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	2.00	2.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X22, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
B.GE 4311d4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W10, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR W11, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD W9, W8, W22, WZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD W10, W10, W22, WZR	1	0	0	0	0	1	0	0	0	0	2	1
CMP W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W10, W11, W10, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W10, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 431180 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X2, X10, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X8, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [X20, #784]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X8, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
BL 404cd0 <@plt_start@+0x6e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	1	0.50
LDR W8, [X20, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 431180 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code