OV - exec - Loop 404

	Loop Id: 404	Module: exec	Source: BsplineFunctor.h:246-260	Coverage: 0.04%

0x41ad40 LD1D	{Z4.D}, P0/Z, [X11, X1,LSL #3]    [4]

0x41ad44 ADD	X1, X1, X24

0x41ad48 CMP	X17, X1

0x41ad4c FMUL	Z4.D, Z4.D, Z26.D

0x41ad50 MOVPRFX	Z5, Z4

0x41ad54 FCVTZS	Z5.D, P0/M, Z4.D

0x41ad58 MOVPRFX	Z6, Z5

0x41ad5c SCVTF	Z6.D, P0/M, Z5.D

0x41ad60 LD1D	{Z16.D}, P0/Z, [X16, Z5.D,LSL #3]    [3]

0x41ad64 MOVPRFX	Z18, Z5

0x41ad68 ADD	Z18.D, Z18.D, #1

0x41ad6c LD1D	{Z18.D}, P0/Z, [X16, Z18.D,SXTW #3]    [5]

0x41ad70 MOVPRFX	Z20, Z5

0x41ad74 ADD	Z20.D, Z20.D, #2

0x41ad78 LD1D	{Z20.D}, P0/Z, [X16, Z20.D,SXTW #3]    [1]

0x41ad7c ADD	Z5.D, Z5.D, #3

0x41ad80 LD1D	{Z5.D}, P0/Z, [X16, Z5.D,SXTW #3]    [2]

0x41ad84 FSUB	Z4.D, Z4.D, Z6.D

0x41ad88 MOVPRFX	Z17, Z30

0x41ad8c FMLA	Z17.D, P0/M, Z4.D, Z29.D

0x41ad90 MOVPRFX	Z19, Z11

0x41ad94 FMLA	Z19.D, P0/M, Z4.D, Z10.D

0x41ad98 MOVPRFX	Z21, Z15

0x41ad9c FMLA	Z21.D, P0/M, Z4.D, Z14.D

0x41ada0 FMUL	Z6.D, Z4.D, Z4.D

0x41ada4 FMLA	Z17.D, P0/M, Z6.D, Z28.D

0x41ada8 FMUL	Z7.D, Z6.D, Z4.D

0x41adac FMLA	Z19.D, P0/M, Z6.D, Z9.D

0x41adb0 FMLA	Z21.D, P0/M, Z6.D, Z13.D

0x41adb4 FMAD	Z4.D, P0/M, Z1.D, Z2.D

0x41adb8 FMLA	Z17.D, P0/M, Z7.D, Z27.D

0x41adbc FMLA	Z19.D, P0/M, Z7.D, Z31.D

0x41adc0 FMLA	Z21.D, P0/M, Z7.D, Z12.D

0x41adc4 FMLA	Z4.D, P0/M, Z6.D, Z0.D

0x41adc8 FMLA	Z3.D, P0/M, Z17.D, Z16.D

0x41adcc FMLA	Z4.D, P0/M, Z7.D, Z8.D

0x41add0 FMLA	Z3.D, P0/M, Z19.D, Z18.D

0x41add4 FMLA	Z3.D, P0/M, Z21.D, Z20.D

0x41add8 FMLA	Z3.D, P0/M, Z4.D, Z5.D

0x41addc B.NE	41ad40

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	16.00
P6 cycles	16.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.95
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	98.03
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	92.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	16.00
P6 cycles	16.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.95
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	98.03
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	92.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences
SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	0.00	0.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	10.00	10.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.00
Data deps.	8.00
Overall L1	16.00

Vectorization ratios

INT

all	52%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	78%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ad40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z4.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
FMUL Z4.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z5.D, P0/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z6, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SCVTF Z6.D, P0/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	3	1
LD1D {Z16.D}, P0/Z, [X16, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z18.D, Z18.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X16, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z20, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z20.D, Z20.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X16, Z20.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z5.D, Z5.D, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z5.D}, P0/Z, [X16, Z5.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z17, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z17.D, P0/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z19, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z19.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z21, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z21.D, P0/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z17.D, P0/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z7.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z19.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P0/M, Z6.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z4.D, P0/M, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z17.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z19.D, P0/M, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P0/M, Z7.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z7.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
B.NE 41ad40 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 1 occurrences
SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

68: addition or subtraction (64 inside FMA instructions)
76: multiply (64 inside FMA instructions)

The binary loop is loading 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	0.00	0.00	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	10.00	10.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.00
Data deps.	8.00
Overall L1	16.00

Vectorization ratios

INT

all	52%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	78%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ad40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z4.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
FMUL Z4.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FCVTZS Z5.D, P0/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	3	1
MOVPRFX Z6, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
SCVTF Z6.D, P0/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	3	1
LD1D {Z16.D}, P0/Z, [X16, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z18.D, Z18.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X16, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z20, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z20.D, Z20.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X16, Z20.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z5.D, Z5.D, #3	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
LD1D {Z5.D}, P0/Z, [X16, Z5.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVPRFX Z17, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z17.D, P0/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z19, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z19.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
MOVPRFX Z21, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z21.D, P0/M, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z17.D, P0/M, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z7.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z19.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P0/M, Z6.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z4.D, P0/M, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z17.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z19.D, P0/M, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P0/M, Z7.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z7.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z3.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
B.NE 41ad40 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code