OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::stop()	Module: exec	Source: NewTimer.cpp:85-120 [...]	Coverage: 0.02%

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/tuple: 193 - 193

--------------------------------------------------------------------------------

193:       : _M_head_impl(__h) { }

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 85 - 120

--------------------------------------------------------------------------------

85: {

86:   if (active)

[...]

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_map.h: 509 - 511

--------------------------------------------------------------------------------

509: 	if (__i == end() || key_comp()(__k, (*__i).first))

510: #if __cplusplus >= 201103L

511: 	  __i = _M_t._M_emplace_hint_unique(__i, std::piecewise_construct,

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_tree.h: 737 - 1953

--------------------------------------------------------------------------------

737:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

782:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

790:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1952:       while (__x != 0)

1953: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 119

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/chrono.h: 212 - 941

--------------------------------------------------------------------------------

212: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

707: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

[...]

941: 	{ return __d; }

0x46c800 SUB	SP, SP, #64

0x46c804 STR	D8, [SP, #16]

0x46c808 STP	X29, X30, [SP, #24]

0x46c80c STR	X21, [SP, #40]

0x46c810 STP	X20, X19, [SP, #48]

0x46c814 ADD	X29, SP, #24

0x46c818 LDRB	W8, [X0, #56]

0x46c81c CBZ	W8, 46ca2c

0x46c820 ORR	X19, XZR, X0

0x46c824 BL	404940

0x46c828 CMP	W0, #1

0x46c82c B.LT	46c860

0x46c830 ORR	W20, WZR, W0

0x46c834 MOVZ	W21, #1

0x46c838 HINT	#0

0x46c83c HINT	#0

(1943) 0x46c840 ORR	W0, WZR, W20

(1943) 0x46c844 BL	404950

(1943) 0x46c848 CMP	W0, #0

(1943) 0x46c84c CSINC	W8, WZR, WZR, #1

(1943) 0x46c850 SUBS	W20, W20, #1

(1943) 0x46c854 AND	W21, W8, W21

(1943) 0x46c858 B.HI	46c840

0x46c85c TBZ	W21, #0, 46ca2c

0x46c860 BL	4049c0

0x46c864 LDR	X8, [X19]

0x46c868 LDR	X10, [X19, #120]

0x46c86c ADD	X20, X19, #80

0x46c870 ADD	X1, X19, #112

0x46c874 SUB	X8, X0, X8

0x46c878 SCVTF	D0, X8

0x46c87c ADRP	X8,

0x46c880 LDR	D1, [X8, #1816]

0x46c884 LDR	X8, [X19, #16]

0x46c888 ADD	X8, X8, #1

0x46c88c STR	X8, [X19, #16]

0x46c890 FMUL	D8, D0, D1

0x46c894 LDR	D0, [X19, #8]

0x46c898 FADD	D0, D8, D0

0x46c89c STR	D0, [X19, #8]

0x46c8a0 CBZ	X10, 46c934

0x46c8a4 LDP	X8, X9, [X19, #80]

0x46c8a8 ORR	X0, XZR, X1

0x46c8ac B	46c8d0

0x46c8b0 HINT	#0

0x46c8b4 HINT	#0

0x46c8b8 HINT	#0

0x46c8bc HINT	#0

(1941) 0x46c8c0 ADD	X11, X10, #16

(1941) 0x46c8c4 ORR	X0, XZR, X10

(1941) 0x46c8c8 LDR	X10, [X11]

(1941) 0x46c8cc CBZ	X10, 46c904

  (1942) 0x46c8d0 LDR	X11, [X10, #32]

  (1942) 0x46c8d4 ORR	X12, XZR, X8

  (1942) 0x46c8d8 CMP	X11, X8

  (1942) 0x46c8dc B.NE	46c8f0

  (1942) 0x46c8e0 LDR	X11, [X10, #40]

  (1942) 0x46c8e4 ORR	X12, XZR, X9

  (1942) 0x46c8e8 CMP	X11, X9

  (1942) 0x46c8ec B.EQ	46c8c0

  (1942) 0x46c8f0 CMP	X11, X12

  (1942) 0x46c8f4 B.GE	46c8c0

  (1942) 0x46c8f8 ADD	X11, X10, #24

  (1942) 0x46c8fc LDR	X10, [X11]

  (1942) 0x46c900 CBNZ	X10, 46c8d0

0x46c904 CMP	X0, X1

0x46c908 B.EQ	46c934

0x46c90c LDR	X10, [X0, #32]

0x46c910 CMP	X8, X10

0x46c914 B.NE	46c928

0x46c918 LDR	X10, [X0, #40]

0x46c91c ORR	X8, XZR, X9

0x46c920 CMP	X9, X10

0x46c924 B.EQ	46c950

0x46c928 ORR	X1, XZR, X0

0x46c92c CMP	X8, X10

0x46c930 B.GE	46c950

0x46c934 ADD	X0, X19, #104

0x46c938 ADRP	X2,

0x46c93c ADD	X2, X2, #710

0x46c940 ADD	X3, SP, #8

0x46c944 STR	X20, [SP, #8]

0x46c948 ADD	X4, SP, #0

0x46c94c BL	46ca50

0x46c950 LDR	D0, [X0, #56]

0x46c954 ADD	X1, X19, #160

0x46c958 FADD	D0, D0, D8

0x46c95c STR	D0, [X0, #56]

0x46c960 LDR	X10, [X19, #168]

0x46c964 CBZ	X10, 46c9f4

0x46c968 LDP	X8, X9, [X19, #80]

0x46c96c ORR	X0, XZR, X1

0x46c970 B	46c990

0x46c974 HINT	#0

0x46c978 HINT	#0

0x46c97c HINT	#0

(1939) 0x46c980 ADD	X11, X10, #16

(1939) 0x46c984 ORR	X0, XZR, X10

(1939) 0x46c988 LDR	X10, [X11]

(1939) 0x46c98c CBZ	X10, 46c9c4

  (1940) 0x46c990 LDR	X11, [X10, #32]

  (1940) 0x46c994 ORR	X12, XZR, X8

  (1940) 0x46c998 CMP	X11, X8

  (1940) 0x46c99c B.NE	46c9b0

  (1940) 0x46c9a0 LDR	X11, [X10, #40]

  (1940) 0x46c9a4 ORR	X12, XZR, X9

  (1940) 0x46c9a8 CMP	X11, X9

  (1940) 0x46c9ac B.EQ	46c980

  (1940) 0x46c9b0 CMP	X11, X12

  (1940) 0x46c9b4 B.GE	46c980

  (1940) 0x46c9b8 ADD	X11, X10, #24

  (1940) 0x46c9bc LDR	X10, [X11]

  (1940) 0x46c9c0 CBNZ	X10, 46c990

0x46c9c4 CMP	X0, X1

0x46c9c8 B.EQ	46c9f4

0x46c9cc LDR	X10, [X0, #32]

0x46c9d0 CMP	X8, X10

0x46c9d4 B.NE	46c9e8

0x46c9d8 LDR	X10, [X0, #40]

0x46c9dc ORR	X8, XZR, X9

0x46c9e0 CMP	X9, X10

0x46c9e4 B.EQ	46ca10

0x46c9e8 ORR	X1, XZR, X0

0x46c9ec CMP	X8, X10

0x46c9f0 B.GE	46ca10

0x46c9f4 ADD	X0, X19, #152

0x46c9f8 ADRP	X2,

0x46c9fc ADD	X2, X2, #710

0x46ca00 ADD	X3, SP, #8

0x46ca04 STR	X20, [SP, #8]

0x46ca08 ADD	X4, SP, #0

0x46ca0c BL	46cef0

0x46ca10 LDR	X8, [X0, #56]

0x46ca14 ADD	X8, X8, #1

0x46ca18 STR	X8, [X0, #56]

0x46ca1c LDR	X0, [X19, #72]

0x46ca20 CBZ	X0, 46ca2c

0x46ca24 ORR	X1, XZR, X19

0x46ca28 BL	472100

0x46ca2c LDR	D8, [SP, #16]

0x46ca30 LDP	X20, X19, [SP, #48]

0x46ca34 LDR	X21, [SP, #40]

0x46ca38 LDP	X29, X30, [SP, #24]

0x46ca3c ADD	SP, SP, #64

0x46ca40 RET

0x46ca44 HINT	#0

0x46ca48 HINT	#0

0x46ca4c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/tuple:193
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_map.h:509-511
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_tree.h:737,782,790,1952-1953
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/chrono.h:212,707,941

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.88 to 2.50 cycles (4.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 11.88 to 2.16 cycles (5.51x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.88 to 2.50 cycles (4.75x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 185 bytes. The binary function is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	11.25	11.25	11.25	11.25	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50
cycles	11.00	11.00	11.25	11.25	11.25	11.25	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	11.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.88 cycles. At this rate:

16% of peak load performance is reached (15.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46c800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W8, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404940 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46c860 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
TBZ W21, #0, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4049c0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X19, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADRP X8, <4b487c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D8, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D0, D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X19, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X10, 46c934 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46c8d0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c934 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46c928 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c950 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46c950 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b5938>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #710	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 46ca50 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_dESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X0, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X10, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 46c9f4 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46c990 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c9f4 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46c9e8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46ca10 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46ca10 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b59f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #710	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 46cef0 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_lESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 472100 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/tuple:193
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_map.h:509-511
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_tree.h:737,782,790,1952-1953
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/chrono.h:212,707,941

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.88 to 2.50 cycles (4.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.88 to 2.50 cycles (4.75x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 185 bytes. The binary function is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	11.25	11.25	11.25	11.25	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50
cycles	11.00	11.00	11.25	11.25	11.25	11.25	1.50	1.50	1.50	1.50	10.00	10.00	10.00	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	11.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.88 cycles. At this rate:

16% of peak load performance is reached (15.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46c800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRB W8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W8, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 404940 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46c860 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
TBZ W21, #0, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4049c0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X19, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADRP X8, <4b487c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8, #1816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D8, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D0, D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X19, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X10, 46c934 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46c8d0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c934 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46c928 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c950 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46c950 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b5938>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #710	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 46ca50 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_dESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X0, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X10, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 46c9f4 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X0, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46c990 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46c9f4 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46c9e8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 46ca10 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46ca10 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X19, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b59f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #710	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 46cef0 <_ZNSt8_Rb_treeIN11qmcplusplus13StackKeyParamILi2EEESt4pairIKS2_lESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 46ca2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 472100 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.02	0.04
▼Loop 1939 - stl_tree.h:782-1953 - exec–	0	0
○Loop 1940 - stl_tree.h:790-1953 - exec	0	0.09
▼Loop 1941 - stl_tree.h:782-1953 - exec–	0	0
○Loop 1942 - stl_tree.h:790-1953 - exec	0	0.16
○Loop 1943 - NewTimer.cpp:99-100 - exec	0	0

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code