OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::acceptMove(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::accept ...	Module: exec	Source: DiracDeterminantRef.cpp:124-139 [...]	Coverage: 0.15%

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h: 23 - 23

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23:   return T((sign_v > 0) ? 0.0 : M_PI);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

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217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/std_abs.h: 72 - 72

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72:   { return __builtin_fabs(__x); }

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 53 - 53

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53:   std::memcpy(target, source, sizeof(T) * n);

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 248 - 248

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248:   inline pointer data() { return X; }

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 124 - 139

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124: {

125:   const int WorkingIndex = iat - FirstIndex;

126:   PhaseValue += evaluatePhase(curRatio);

127:   LogValue += std::log(std::abs(curRatio));

128:   UpdateTimer->start();

129:   updateEng.acceptRow(psiM, WorkingIndex, psiV);

130:   // invRow becomes invalid after accepting a move

131:   invRow_id = -1;

132:   if (UpdateMode == ORB_PBYP_PARTIAL)

133:   {

134:     simd::copy(dpsiM[WorkingIndex], dpsiV.data(), NumOrbitals);

135:     simd::copy(d2psiM[WorkingIndex], d2psiV.data(), NumOrbitals);

136:   }

137:   UpdateTimer->stop();

138:   curRatio = 1.0;

139: }

0x43aa80 SUB	SP, SP, #64

0x43aa84 STP	X29, X30, [SP, #16]

0x43aa88 STR	X21, [SP, #32]

0x43aa8c STP	X20, X19, [SP, #48]

0x43aa90 ADD	X29, SP, #16

0x43aa94 LDRSW	X8, [X0, #1144]

0x43aa98 SBFM	X9, X2, #0, #31

0x43aa9c LDR	D0, [X0, #1080]

0x43aaa0 MOVI	D2, #0

0x43aaa4 ORR	X19, XZR, X0

0x43aaa8 SUB	X20, X9, X8

0x43aaac ADRP	X8,

0x43aab0 LDR	D1, [X8, #3264]

0x43aab4 FCMP	D0, #0

0x43aab8 FABS	D0, D0

0x43aabc FCSEL	D1, D2, D1, #12

0x43aac0 STR	Q1, [SP]

0x43aac4 BL	404b80

0x43aac8 LDR	Q2, [SP]

0x43aacc LDR	Q1, [X19, #16]

0x43aad0 LDR	X0, [X19, #1088]

0x43aad4 MOV	V0.D[1], V2.D[0]

0x43aad8 FADD	V0.2D, V1.2D, V0.2D

0x43aadc STR	Q0, [X19, #16]

0x43aae0 BL	46c6e0

0x43aae4 ORR	W2, WZR, W20

0x43aae8 ADD	X0, X19, #520

0x43aaec ADD	X1, X19, #208

0x43aaf0 ADD	X3, X19, #400

0x43aaf4 BL	438d20

0x43aaf8 MOVN	W8, #0

0x43aafc STR	W8, [X19, #1072]

0x43ab00 LDR	W8, [X19, #12]

0x43ab04 CMP	W8, #2

0x43ab08 B.NE	43abb4

0x43ab0c LDR	X9, [X19, #280]

0x43ab10 LDR	X8, [X19, #320]

0x43ab14 MOVZ	W10, #24

0x43ab18 LDR	X1, [X19, #464]

0x43ab1c RDVL	X21, #1

0x43ab20 CMP	X21, #17

0x43ab24 MADD	X9, X9, X20, XZR

0x43ab28 MADD	X0, X9, X10, X8

0x43ab2c LDRSW	X8, [X19, #1152]

0x43ab30 ADD	X8, X8, X8,LSL #1

0x43ab34 UBFM	X2, X8, #61, #60

0x43ab38 B.CS	43ab44

0x43ab3c BL	404700

0x43ab40 B	43ab60

0x43ab44 WHILELO	P0.B, XZR, X2

0x43ab48 ORR	X8, XZR, XZR

(1092) 0x43ab4c LD1B	{Z0.B}, P0/Z, [X1, X8]

(1092) 0x43ab50 ST1B	{Z0.B}, P0, [X0, X8]

(1092) 0x43ab54 INCP	X8, P0.B

(1092) 0x43ab58 WHILELO	P0.B, X8, X2

(1092) 0x43ab5c B.MI	43ab4c

0x43ab60 LDR	X9, [X19, #344]

0x43ab64 LDR	X8, [X19, #384]

0x43ab68 LDR	X1, [X19, #504]

0x43ab6c CMP	X21, #17

0x43ab70 MADD	X9, X9, X20, XZR

0x43ab74 ADD	X0, X8, X9,LSL #3

0x43ab78 LDRSW	X8, [X19, #1152]

0x43ab7c UBFM	X2, X8, #61, #60

0x43ab80 B.CS	43ab8c

0x43ab84 BL	404700

0x43ab88 B	43abb4

0x43ab8c WHILELO	P0.B, XZR, X2

0x43ab90 ORR	X8, XZR, XZR

0x43ab94 HINT	#0

0x43ab98 HINT	#0

0x43ab9c HINT	#0

(1093) 0x43aba0 LD1B	{Z0.B}, P0/Z, [X1, X8]

(1093) 0x43aba4 ST1B	{Z0.B}, P0, [X0, X8]

(1093) 0x43aba8 INCP	X8, P0.B

(1093) 0x43abac WHILELO	P0.B, X8, X2

(1093) 0x43abb0 B.MI	43aba0

0x43abb4 LDR	X0, [X19, #1088]

0x43abb8 BL	46c800

0x43abbc MOVZ	X8, #16368

0x43abc0 STR	X8, [X19, #1080]

0x43abc4 LDP	X20, X19, [SP, #48]

0x43abc8 LDR	X21, [SP, #32]

0x43abcc LDP	X29, X30, [SP, #16]

0x43abd0 ADD	SP, SP, #64

0x43abd4 RET

0x43abd8 HINT	#0

0x43abdc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:124-139
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h:23
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/std_abs.h:72
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:53
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:124-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.13 to 2.00 cycles (4.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 9.13 to 1.69 cycles (5.41x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
20% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.13 to 3.00 cycles (3.04x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 168 bytes. The binary function is storing 84 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	8.75	8.75	8.75	8.75	2.00	2.00	2.00	2.00	8.83	8.50	8.67	2.50	2.50
cycles	6.00	6.00	8.75	8.75	8.75	8.75	2.00	2.00	2.00	2.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Overall L1	9.13

Vectorization ratios

INT

all	21%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.13 cycles. At this rate:

19% of peak load performance is reached (18.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43aa80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X0, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X8, <4b5aac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8, #3264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D1, D2, D1, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Q1, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 404b80 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR Q2, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR Q1, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOV V0.D[1], V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR Q0, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 46c6e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 438d20 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43abb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
RDVL X21, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X21, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDRSW X8, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X8,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 43ab44 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404700 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43ab60 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X0, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 43ab8c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404700 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43abb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 46c800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X8, #16368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	DiracDeterminantRef.cpp:124-139
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h:23
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/std_abs.h:72
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:53
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:124-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.13 to 2.00 cycles (4.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
20% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.13 to 3.00 cycles (3.04x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 168 bytes. The binary function is storing 84 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	8.75	8.75	8.75	8.75	2.00	2.00	2.00	2.00	8.83	8.50	8.67	2.50	2.50
cycles	6.00	6.00	8.75	8.75	8.75	8.75	2.00	2.00	2.00	2.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Overall L1	9.13

Vectorization ratios

INT

all	21%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	50%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.13 cycles. At this rate:

19% of peak load performance is reached (18.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43aa80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X0, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X8, <4b5aac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8, #3264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCSEL D1, D2, D1, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Q1, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 404b80 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR Q2, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR Q1, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOV V0.D[1], V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR Q0, [X19, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 46c6e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X19, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 438d20 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43abb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
RDVL X21, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X21, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDRSW X8, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X8,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 43ab44 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404700 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43ab60 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X0, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X8, [X19, #1152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 43ab8c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 404700 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43abb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 46c800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X8, #16368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)–	0.15	0.24
○Loop 1092 - inner_product.hpp:53-53 - exec	0.1	0.14
○Loop 1093 - inner_product.hpp:53-53 - exec	0.05	0.06

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code