OV - exec - Loop 1442

0x46ceb4 ADD	X12, X1, #48

0x46ceb8 ADD	X9, X1, #96

0x46cebc STP	Q0, Q0, [X1]    [7]

0x46cec0 STP	Q0, Q0, [X1, #32]    [7]

0x46cec4 STP	Q0, Q0, [X12, #16]    [4]

0x46cec8 STR	Q0, [X1, #96]    [7]

0x46cecc ADD	X8, X1, #144

0x46ced0 ADD	X10, X1, #192

0x46ced4 STP	Q0, Q0, [X9, #16]    [8]

0x46ced8 STR	Q0, [X1, #144]    [7]

0x46cedc ADD	X6, X1, #240

0x46cee0 ADD	X11, X1, #288

0x46cee4 STP	Q0, Q0, [X8, #16]    [5]

0x46cee8 STR	Q0, [X1, #192]    [7]

0x46ceec ADD	X13, X1, #336

0x46cef0 ADD	X1, X1, #384

0x46cef4 STP	Q0, Q0, [X10, #16]    [1]

0x46cef8 STUR	Q0, [X1, #368]    [9]

0x46cefc STP	Q0, Q0, [X6, #16]    [2]

0x46cf00 STUR	Q0, [X1, #416]    [9]

0x46cf04 STP	Q0, Q0, [X11, #16]    [3]

0x46cf08 STUR	Q0, [X1, #464]    [9]

0x46cf0c STP	Q0, Q0, [X13, #16]    [6]

0x46cf10 CMP	X30, X1

0x46cf14 B.NE	46ceb4

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 939 - 940

--------------------------------------------------------------------------------

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P6, P7, P10, P11,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	stl_algobase.h:939-940
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	6.00
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	51.20
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	384.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	80.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	80.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P6, P7, P10, P11,
Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source	stl_algobase.h:939-940
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	6.00
Front-end cycles	3.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	51.20
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	384.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	80.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	80.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:939-940
Module	exec

The loop is defined in /home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:939-940.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 80% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 384 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	7.50	7.50	0.00	0.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	7.50	7.50	0.00	0.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

106% of peak store performance is reached (51.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46ceb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
ADD X12, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X9, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X1, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X12, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X8, X1, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X10, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X9, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X6, X1, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X11, X1, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X8, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #192]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X13, X1, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X1, X1, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #368]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X6, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X11, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X13, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 46ceb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::resize(int, int)
Source file and lines	stl_algobase.h:939-940
Module	exec

The loop is defined in /home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:939-940.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 80% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 384 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	7.50	7.50	0.00	0.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	7.50	7.50	0.00	0.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

106% of peak store performance is reached (51.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46ceb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
ADD X12, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X9, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X1, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X12, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X8, X1, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X10, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X9, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X6, X1, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X11, X1, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X8, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X1, #192]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X13, X1, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X1, X1, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP Q0, Q0, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #368]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X6, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X11, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STUR Q0, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X13, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 46ceb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE6resizeEii+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code