OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGrad(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGr ...	Module: exec	Source: DiracDeterminantRef.cpp:82-91 [...]	Coverage: 0.3%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 98 - 113

--------------------------------------------------------------------------------

98:     if (delay_count == 0)

99:     {

100:       // Ainv is fresh, directly access Ainv

101:       std::copy_n(Ainv[rowchanged], invRow.size(), invRow.data());

102:       return;

103:     }

104:     const T cone(1);

105:     const T czero(0);

106:     const int norb     = Ainv.rows();

107:     const int lda_Binv = Binv.cols();

108:     // save Ainv[rowchanged] to invRow

109:     std::copy_n(Ainv[rowchanged], norb, invRow.data());

110:     // multiply V (NxK) Binv(KxK) U(KxN) invRow right to the left

111:     BLAS::gemv('T', norb, delay_count, cone, U.data(), norb, invRow.data(), 1, czero, p.data(), 1);

112:     BLAS::gemv('N', delay_count, delay_count, cone, Binv.data(), lda_Binv, p.data(), 1, czero, Binv[delay_count], 1);

113:     BLAS::gemv('N', norb, delay_count, -cone, V.data(), norb, Binv[delay_count], 1, cone, invRow.data(), 1);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

--------------------------------------------------------------------------------

77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

214:   inline const Type_t* operator[](size_type i) const { return X.data() + i * D2; }

215:

216:   /// returns a pointer of i-th row, g++ iterator problem

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 156

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 82 - 91

--------------------------------------------------------------------------------

82: typename DiracDeterminantRef<DU_TYPE>::GradType DiracDeterminantRef<DU_TYPE>::evalGrad(ParticleSet& P, int iat)

83: {

84:   const int WorkingIndex = iat - FirstIndex;

85:   RatioTimer->start();

86:   invRow_id = WorkingIndex;

87:   updateEng.getInvRow(psiM, WorkingIndex, invRow);

88:   GradType g = simd::dot(invRow.data(), dpsiM[WorkingIndex], invRow.size());

89:   RatioTimer->stop();

90:   return g;

91: }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h: 413 - 453

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

0x466fc0 SUB	SP, SP, #272

0x466fc4 STP	X29, X30, [SP, #32]

0x466fc8 ADD	X29, SP, #32

0x466fcc STP	X19, X20, [SP, #48]

0x466fd0 ORR	X19, XZR, X0

0x466fd4 STP	X21, X22, [SP, #64]

0x466fd8 STP	X25, X26, [SP, #96]

0x466fdc ADD	X25, X0, #520

0x466fe0 LDR	W1, [X0, #1144]

0x466fe4 LDR	X0, [X0, #1096]

0x466fe8 STR	D15, [SP, #128]

0x466fec SUB	W20, W2, W1

0x466ff0 BL	4c43c0

0x466ff4 LDR	X4, [X19, #216]

0x466ff8 SBFM	X21, X20, #0, #31

0x466ffc STR	W20, [X19, #1072]

0x467000 LDR	X5, [X19, #256]

0x467004 LDR	W8, [X25, #360]

0x467008 MADD	X0, X21, X4, XZR

0x46700c UBFM	X7, X0, #61, #60

0x467010 ADD	X1, X5, X7

0x467014 CBZ	W8, 467394

0x467018 STP	X27, X28, [SP, #112]

0x46701c ADD	X28, X19, #648

0x467020 STP	X23, X24, [SP, #80]

0x467024 ADD	X24, X19, #1032

0x467028 LDR	X2, [X28, #8]

0x46702c LDR	X23, [X19, #208]

0x467030 LDR	X6, [X24, #24]

0x467034 STR	X2, [SP, #144]

0x467038 CMP	W23, #0

0x46703c B.LE	46705c

0x467040 UBFM	X2, X23, #61, #31

0x467044 CMP	X2, #8

0x467048 B.EQ	4673d8

0x46704c ORR	X0, XZR, X6

0x467050 BL	403a40

0x467054 LDR	X6, [X24, #24]

0x467058 LDR	W8, [X25, #360]

0x46705c FMOV	D15, #1.0000000

0x467060 MOVZ	W26, #1

0x467064 ADD	X27, SP, #228

0x467068 LDR	X9, [X19, #840]

0x46706c ADD	X22, SP, #240

0x467070 MOVZ	W3, #84

0x467074 ADD	X7, SP, #224

0x467078 ADD	X5, SP, #220

0x46707c STR	X27, [SP, #16]

0x467080 ADD	X2, SP, #216

0x467084 ADD	X0, SP, #211

0x467088 STRB	W3, [SP, #211]

0x46708c ADD	X1, SP, #212

0x467090 ADD	X3, SP, #232

0x467094 STP	W23, W8, [SP, #212]

0x467098 STP	W23, W26, [SP, #220]

0x46709c LDR	X4, [X19, #568]

0x4670a0 STP	X22, X9, [SP]

0x4670a4 STR	W26, [SP, #228]

0x4670a8 STR	D15, [SP, #232]

0x4670ac STR	XZR, [SP, #240]

0x4670b0 BL	403cf0

0x4670b4 LDR	W6, [X25, #360]

0x4670b8 MOVZ	W11, #78

0x4670bc ADD	X12, X19, #672

0x4670c0 STR	X22, [SP]

0x4670c4 ADD	X7, SP, #224

0x4670c8 ADD	X5, SP, #220

0x4670cc LDR	W13, [SP, #144]

0x4670d0 ADD	X3, SP, #232

0x4670d4 ADD	X2, SP, #216

0x4670d8 ADD	X1, SP, #212

0x4670dc ADD	X0, SP, #211

0x4670e0 STR	W11, [SP, #164]

0x4670e4 STR	X12, [SP, #168]

0x4670e8 STP	W6, W6, [SP, #212]

0x4670ec SBFM	X10, X6, #0, #31

0x4670f0 STRB	W11, [SP, #211]

0x4670f4 STP	W13, W26, [SP, #220]

0x4670f8 LDR	X14, [X28, #8]

0x4670fc STR	X27, [SP, #16]

0x467100 LDR	X4, [X19, #696]

0x467104 STR	W26, [SP, #228]

0x467108 LDR	X6, [X19, #840]

0x46710c MADD	X15, X10, X14, XZR

0x467110 STR	D15, [SP, #232]

0x467114 STR	XZR, [SP, #240]

0x467118 ADD	X18, X4, X15,LSL #3

0x46711c STR	X18, [SP, #8]

0x467120 BL	403cf0

0x467124 LDR	W25, [X25, #360]

0x467128 FMOV	D0, #-1.0000000

0x46712c ADD	X3, SP, #232

0x467130 STR	X22, [SP]

0x467134 ADD	X0, SP, #211

0x467138 ADD	X7, SP, #224

0x46713c LDR	X8, [SP, #168]

0x467140 ADD	X5, SP, #220

0x467144 ADD	X2, SP, #216

0x467148 STP	W23, W26, [SP, #220]

0x46714c ADD	X1, SP, #212

0x467150 STP	D0, D15, [SP, #232]

0x467154 STP	W23, W25, [SP, #212]

0x467158 SBFM	X20, X25, #0, #31

0x46715c LDR	X28, [X28, #8]

0x467160 STR	W26, [SP, #228]

0x467164 LDR	X23, [X8, #24]

0x467168 LDR	X26, [X24, #24]

0x46716c MADD	X22, X20, X28, XZR

0x467170 LDR	W4, [SP, #164]

0x467174 ADD	X6, X23, X22,LSL #3

0x467178 STP	X26, X27, [SP, #8]

0x46717c STRB	W4, [SP, #211]

0x467180 LDR	X4, [X19, #632]

0x467184 BL	403cf0

0x467188 LDR	X3, [X24, #8]

0x46718c LDP	X27, X28, [SP, #112]

0x467190 LDR	X0, [X24, #24]

0x467194 LDP	X23, X24, [SP, #80]

(1375) 0x467198 ORR	W16, WZR, W3

(1375) 0x46719c LDR	X17, [X19, #280]

(1375) 0x4671a0 LDR	X30, [X19, #320]

(1375) 0x4671a4 MADD	X21, X21, X17, XZR

(1375) 0x4671a8 CMP	W3, #0

(1375) 0x4671ac B.LE	4673bc

(1375) 0x4671b0 SUB	W1, W3, #1

(1375) 0x4671b4 ORR	W5, WZR, W3

(1375) 0x4671b8 CMP	W1, #2

(1375) 0x4671bc B.LS	4673c8

(1375) 0x4671c0 ADD	X9, X21, X21,LSL #1

(1375) 0x4671c4 UBFM	W12, W3, #2, #31

(1375) 0x4671c8 MOVZ	W2, #96

(1375) 0x4671cc MOVI	V26.2D, #0

(1375) 0x4671d0 ORR	X10, XZR, X0

(1375) 0x4671d4 ADD	X14, X30, X9,LSL #3

(1375) 0x4671d8 UMADDL	X11, W12, W2, X14

(1375) 0x4671dc ORR	V4.16B, V26.16B, V26.16B

(1375) 0x4671e0 ORR	V22.16B, V26.16B, V26.16B

(1375) 0x4671e4 ORR	V3.16B, V26.16B, V26.16B

(1375) 0x4671e8 ORR	V19.16B, V26.16B, V26.16B

(1375) 0x4671ec ORR	V5.16B, V26.16B, V26.16B

(1375) 0x4671f0 SUB	X6, X11, X14

(1375) 0x4671f4 TBZ	W6, #5, 467230

(1375) 0x4671f8 LDP	Q28, Q29, [X0]

(1375) 0x4671fc ADD	X10, X0, #32

(1375) 0x467200 LDP	Q2, Q25, [X14, #16]

(1375) 0x467204 LDP	Q24, Q30, [X14, #48]

(1375) 0x467208 LDR	Q27, [X14, #80]

(1375) 0x46720c LDR	Q6, [X14], #96

(1375) 0x467210 FMLA	V19.2D, V28.2D, V2.2D

(1375) 0x467214 FMLA	V3.2D, V25.2D, V28.D[1]

(1375) 0x467218 FMLA	V22.2D, V24.2D, V29.D[0]

(1375) 0x46721c FMLA	V4.2D, V29.2D, V30.2D

(1375) 0x467220 FMLA	V5.2D, V6.2D, V28.D[0]

(1375) 0x467224 FMLA	V26.2D, V27.2D, V29.D[1]

(1375) 0x467228 CMP	X14, X11

(1375) 0x46722c B.EQ	467298

  (1376) 0x467230 ORR	X13, XZR, X14

  (1376) 0x467234 LDP	Q16, Q17, [X10]

  (1376) 0x467238 LDR	Q7, [X13], #96

  (1376) 0x46723c LDP	Q18, Q23, [X14, #16]

  (1376) 0x467240 LDP	Q20, Q21, [X14, #48]

  (1376) 0x467244 LDP	Q0, Q1, [X14, #80]

  (1376) 0x467248 ADD	X14, X14, #192

  (1376) 0x46724c FMLA	V5.2D, V7.2D, V16.D[0]

  (1376) 0x467250 LDP	Q28, Q29, [X10, #32]

  (1376) 0x467254 ADD	X10, X10, #64

  (1376) 0x467258 LDP	Q31, Q15, [X13, #16]

  (1376) 0x46725c FMLA	V19.2D, V16.2D, V18.2D

  (1376) 0x467260 LDP	Q2, Q25, [X13, #48]

  (1376) 0x467264 LDR	Q24, [X13, #80]

  (1376) 0x467268 FMLA	V3.2D, V23.2D, V16.D[1]

  (1376) 0x46726c FMLA	V22.2D, V20.2D, V17.D[0]

  (1376) 0x467270 FMLA	V4.2D, V17.2D, V21.2D

  (1376) 0x467274 FMLA	V26.2D, V0.2D, V17.D[1]

  (1376) 0x467278 FMLA	V19.2D, V28.2D, V31.2D

  (1376) 0x46727c FMLA	V3.2D, V15.2D, V28.D[1]

  (1376) 0x467280 FMLA	V22.2D, V2.2D, V29.D[0]

  (1376) 0x467284 FMLA	V4.2D, V29.2D, V25.2D

  (1376) 0x467288 FMLA	V5.2D, V1.2D, V28.D[0]

  (1376) 0x46728c FMLA	V26.2D, V24.2D, V29.D[1]

  (1376) 0x467290 CMP	X14, X11

  (1376) 0x467294 B.NE	467230

(1375) 0x467298 MOV	D27, V3.D[1]

(1375) 0x46729c AND	W7, W5, #1886

(1375) 0x4672a0 EXT	V3.16B, V19.16B, V3.16B, #8

(1375) 0x4672a4 MOV	D6, V26.D[1]

(1375) 0x4672a8 EXT	V26.16B, V4.16B, V26.16B, #8

(1375) 0x4672ac FADD	V30.2D, V5.2D, V22.2D

(1375) 0x4672b0 FADD	D19, D4, D19

(1375) 0x4672b4 FADD	V22.2D, V3.2D, V26.2D

(1375) 0x4672b8 FADD	D4, D27, D6

(1375) 0x4672bc FADD	V31.2D, V22.2D, V30.2D

(1375) 0x4672c0 FADD	D15, D4, D19

(1375) 0x4672c4 ANDS	XZR, X5, #4160

(1375) 0x4672c8 B.EQ	46735c

(1375) 0x4672cc ADD	X15, X21, W7,SXTW

(1375) 0x4672d0 ADD	X18, X15, X15,LSL #1

(1375) 0x4672d4 ORR	W25, WZR, W7

(1375) 0x4672d8 UBFM	X20, X25, #61, #60

(1375) 0x4672dc ADD	W4, W7, #1

(1375) 0x4672e0 UBFM	X8, X18, #61, #60

(1375) 0x4672e4 ADD	X22, X30, X8

(1375) 0x4672e8 LDR	D5, [X0, X20]

(1375) 0x4672ec LDR	Q7, [X30, X8]

(1375) 0x4672f0 LDR	D16, [X22, #16]

(1375) 0x4672f4 FMLA	V31.2D, V7.2D, V5.D[0]

(1375) 0x4672f8 FMADD	D15, D5, D16, D15

(1375) 0x4672fc CMP	W16, W4

(1375) 0x467300 B.LE	46735c

(1375) 0x467304 ADD	X26, X21, W4,SXTW

(1375) 0x467308 ADD	X3, X26, X26,LSL #1

(1375) 0x46730c ADD	X17, X0, X20

(1375) 0x467310 ADD	W1, W7, #2

(1375) 0x467314 UBFM	X0, X3, #61, #60

(1375) 0x467318 LDR	D23, [X17, #8]

(1375) 0x46731c ADD	X5, X30, X0

(1375) 0x467320 LDR	Q17, [X30, X0]

(1375) 0x467324 LDR	D18, [X5, #16]

(1375) 0x467328 FMLA	V31.2D, V17.2D, V23.D[0]

(1375) 0x46732c FMADD	D15, D23, D18, D15

(1375) 0x467330 CMP	W16, W1

(1375) 0x467334 B.LE	46735c

(1375) 0x467338 ADD	X16, X21, W1,SXTW

(1375) 0x46733c ADD	X21, X16, X16,LSL #1

(1375) 0x467340 LDR	D0, [X17, #16]

(1375) 0x467344 UBFM	X7, X21, #61, #60

(1375) 0x467348 ADD	X9, X30, X7

(1375) 0x46734c LDR	Q20, [X30, X7]

(1375) 0x467350 LDR	D21, [X9, #16]

(1375) 0x467354 FMLA	V31.2D, V20.2D, V0.D[0]

(1375) 0x467358 FMADD	D15, D21, D0, D15

(1375) 0x46735c LDR	X0, [X19, #1096]

(1375) 0x467360 STR	Q31, [SP, #144]

(1375) 0x467364 BL	4c4660

(1375) 0x467368 LDR	Q1, [SP, #144]

(1375) 0x46736c FMOV	D2, D15

(1375) 0x467370 LDP	X29, X30, [SP, #32]

(1375) 0x467374 LDP	X19, X20, [SP, #48]

(1375) 0x467378 STR	Q1, [SP, #240]

(1375) 0x46737c LDR	D15, [SP, #128]

(1375) 0x467380 LDP	X21, X22, [SP, #64]

(1375) 0x467384 LDP	X25, X26, [SP, #96]

(1375) 0x467388 LDP	D0, D1, [SP, #240]

(1375) 0x46738c ADD	SP, SP, #272

(1375) 0x467390 RET

(1375) 0x467394 LDR	X3, [X19, #1040]

(1375) 0x467398 CBZ	X3, 4673bc

(1375) 0x46739c UBFM	X2, X3, #61, #60

(1375) 0x4673a0 LDR	X0, [X19, #1056]

(1375) 0x4673a4 CMP	X2, #8

(1375) 0x4673a8 B.LE	4673e4

(1375) 0x4673ac BL	403a40

(1375) 0x4673b0 LDR	X3, [X19, #1040]

(1375) 0x4673b4 LDR	X0, [X19, #1056]

(1375) 0x4673b8 B	467198

(1375) 0x4673bc MOVI	V31.2D, #0

(1375) 0x4673c0 FMOV	D15, D31

(1375) 0x4673c4 B	46735c

(1375) 0x4673c8 MOVI	V31.2D, #0

(1375) 0x4673cc MOVZ	W7, #0

(1375) 0x4673d0 FMOV	D15, D31

(1375) 0x4673d4 B	4672cc

0x4673d8 LDR	D31, [X5, X7]

0x4673dc STR	D31, [X6]

0x4673e0 B	46705c

(1375) 0x4673e4 B.NE	467198

(1375) 0x4673e8 LDR	D1, [X5, X7]

(1375) 0x4673ec STR	D1, [X0]

(1375) 0x4673f0 B	467198

0x4673f4 HINT	#0

0x4673f8 HINT	#0

0x4673fc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	DiracDeterminantRef.cpp:82-91
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:82-91
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 4.17 cycles (5.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.67 to 3.06 cycles (7.07x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
20% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.50 cycles (8.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 319 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.50	12.50	12.50	12.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50
cycles	4.50	4.50	12.50	12.50	12.50	12.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.13
Overall L1	21.67

Vectorization ratios

all	3%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

10% of peak load performance is reached (10.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 466fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X0, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D15, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
SUB W20, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X21, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X21, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X7, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W8, 467394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X19, #648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 46705c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X23, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4673d8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a40 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D15, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, SP, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W3, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W3, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W23, W8, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X22, X9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W11, #78	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X19, #672	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W11, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W6, W6, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X10, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W11, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W13, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #696]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X15, X10, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X18, X4, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W25, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D0, D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP W23, W25, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X20, X25, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X22, X20, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W4, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W4, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X0, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D31, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 46705c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	DiracDeterminantRef.cpp:82-91
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155-156
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:82-91
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_algo.h:683,709
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 4.17 cycles (5.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
20% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.50 cycles (8.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 319 bytes.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.50	12.50	12.50	12.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50
cycles	4.50	4.50	12.50	12.50	12.50	12.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.13
Overall L1	21.67

Vectorization ratios

all	3%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

10% of peak load performance is reached (10.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 466fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X25, X0, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D15, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
SUB W20, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4c43c0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X21, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X21, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X7, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W8, 467394 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X19, #648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X24, X19, #1032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 46705c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X23, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4673d8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403a40 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D15, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, SP, #228	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W3, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W3, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W23, W8, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X22, X9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W11, #78	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X19, #672	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W11, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W6, W6, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X10, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STRB W11, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W13, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #696]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X15, X10, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X18, X4, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W25, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X3, SP, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, SP, #211	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, SP, #220	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, SP, #212	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D0, D15, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP W23, W25, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X20, X25, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X22, X20, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W4, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STRB W4, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 403cf0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X0, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D31, [X5, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 46705c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)–	0.3	0.5
▼Loop 1375 - OhmmsVector.h:178-248 - exec–	0.01	0.01
○Loop 1376 - inner_product.hpp:155-155 - exec	0.29	0.41

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code