OV - exec - Function qmcplusplus::BsplineAllocator<double, 32ul, qmcplusplus::Mallocator<double, 32ul> >::setCoefficientsForOrbitals(int, int, Array<double, 3u>&, multi_UBspline_3d_d*) [clone ._omp

	Function: qmcplusplus::BsplineAllocator<double, 32ul, qmcplusplus::Mallocator<double, 32ul> >::setCo ...	Module: exec	Source: BsplineAllocator.hpp:171-180 [...]	Coverage: 0.04%

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp: 171 - 180

--------------------------------------------------------------------------------

171: #pragma omp parallel for collapse(3)

172:   for (int ix = 0; ix < spline->x_grid.num + 3; ix++)

173:     for (int iy = 0; iy < spline->y_grid.num + 3; iy++)

174:       for (int iz = 0; iz < spline->z_grid.num + 3; iz++)

175:       {

176:         intptr_t xs = spline->x_stride;

177:         intptr_t ys = spline->y_stride;

178:         intptr_t zs = spline->z_stride;

179:         for (int ind = first; ind < last; ind++)

180:           spline->coefs[ix * xs + iy * ys + iz * zs + ind] = coeff(ix, iy, iz) * prefactor[ind];

/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h: 1128 - 1131

--------------------------------------------------------------------------------

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h: 156 - 156

--------------------------------------------------------------------------------

156:     return X[k + Length[2] * (j + Length[1] * i)];

0x450aa0 STP	X29, X30, [SP, #896]!

0x450aa4 ADD	X29, SP, #0

0x450aa8 STP	X19, X20, [SP, #16]

0x450aac STP	X21, X22, [SP, #32]

0x450ab0 ORR	X22, XZR, X0

0x450ab4 STP	X23, X24, [SP, #48]

0x450ab8 LDR	X23, [X0, #8]

0x450abc LDR	W0, [X23, #96]

0x450ac0 LDR	W1, [X23, #56]

0x450ac4 LDR	W19, [X23, #136]

0x450ac8 ADD	W3, W0, #3

0x450acc ADD	W2, W1, #3

0x450ad0 STR	W3, [SP, #116]

0x450ad4 CMP	W2, #0

0x450ad8 B.LE	450ea0

0x450adc CMP	W3, #0

0x450ae0 B.LE	450ea0

0x450ae4 ADD	W19, W19, #3

0x450ae8 MADD	W4, W2, W3, WZR

0x450aec CMP	W19, #0

0x450af0 B.LE	450ea0

0x450af4 MADD	W20, W4, W19, WZR

0x450af8 BL	403c90

0x450afc ORR	W21, WZR, W0

0x450b00 BL	403cc0

0x450b04 UDIV	W14, W20, W21

0x450b08 ORR	W6, WZR, W0

0x450b0c MSUB	W5, W14, W21, W20

0x450b10 CMP	W0, W5

0x450b14 B.CC	4510bc

0x450b18 MADD	W7, W14, W6, W5

0x450b1c ADD	W8, W14, W7

0x450b20 CMP	W7, W8

0x450b24 B.CS	450ea0

0x450b28 UDIV	W9, W7, W19

0x450b2c LDR	W11, [SP, #116]

0x450b30 LDP	W17, W10, [X22, #24]

0x450b34 LDR	X0, [X22]

0x450b38 LDR	X22, [X22, #16]

0x450b3c STR	W10, [SP, #112]

0x450b40 LDR	X21, [X23, #32]

0x450b44 LDP	X30, X20, [X23, #16]

0x450b48 UDIV	W15, W9, W11

0x450b4c MSUB	W6, W9, W19, W7

0x450b50 MSUB	W1, W15, W11, W9

0x450b54 STP	W1, W15, [SP, #120]

0x450b58 CMP	W10, W17

0x450b5c B.LE	450ea0

0x450b60 STP	X25, X26, [SP, #64]

0x450b64 SBFM	X12, X17, #0, #31

0x450b68 SUB	W24, W10, W17

0x450b6c ADD	X18, X12, #1

0x450b70 UBFM	W13, W24, #2, #31

0x450b74 PTRUE	P6.B, ALL

0x450b78 UBFM	X26, X18, #61, #60

0x450b7c SBFM	X16, X15, #0, #31

0x450b80 STP	X27, X28, [SP, #80]

0x450b84 SUB	X27, X26, #8

0x450b88 SUB	W28, W24, #1

0x450b8c AND	W2, W24, #1886

0x450b90 AND	W3, W24, #64

0x450b94 MOVZ	W11, #0

0x450b98 SUB	W14, W14, #1

0x450b9c LDR	X9, [X22]

0x450ba0 UBFM	X13, X13, #59, #58

0x450ba4 SBFM	X15, X1, #0, #31

0x450ba8 ADD	X17, X0, #24

0x450bac STR	W28, [SP, #96]

0x450bb0 LDR	X10, [X23, #8]

0x450bb4 LDP	X22, X23, [X0, #8]

0x450bb8 ADD	X4, X9, X27

0x450bbc ADD	X18, X9, X26

0x450bc0 ADD	X5, X4, #16

0x450bc4 STR	W2, [SP, #100]

0x450bc8 STP	W3, W24, [SP, #104]

  (1134) 0x450bcc SBFM	X7, X6, #0, #31

  (1134) 0x450bd0 MADD	X8, X15, X20, XZR

  (1134) 0x450bd4 MADD	X1, X16, X22, X15

  (1134) 0x450bd8 MADD	X28, X7, X21, XZR

  (1134) 0x450bdc MADD	X3, X16, X30, X8

  (1134) 0x450be0 MADD	X0, X1, X23, X7

  (1134) 0x450be4 LDR	X7, [X17]

  (1134) 0x450be8 ADD	X25, X28, X12

  (1134) 0x450bec ADD	X2, X3, X25

  (1134) 0x450bf0 ADD	X26, X24, X2

  (1134) 0x450bf4 UBFM	X0, X0, #61, #60

  (1134) 0x450bf8 ADD	X27, X10, X26,LSL #3

  (1134) 0x450bfc ADD	X25, X0, #8

  (1134) 0x450c00 UBFM	X26, X2, #61, #60

  (1134) 0x450c04 ADD	X8, X7, X0

  (1134) 0x450c08 ADD	X1, X10, X26

  (1134) 0x450c0c CMP	X8, X27

  (1134) 0x450c10 ADD	X27, X7, X25

  (1134) 0x450c14 CCMP	X1, X27, #2, #3

  (1134) 0x450c18 SUB	X25, X1, X18

  (1134) 0x450c1c CCMP	X25, #16, #0, #2

  (1134) 0x450c20 B.LS	450efc

  (1134) 0x450c24 LDR	W28, [SP, #96]

  (1134) 0x450c28 CMP	W28, #2

  (1134) 0x450c2c B.LS	4510b4

  (1134) 0x450c30 LDR	D31, [X7, X0]

  (1134) 0x450c34 SUB	X3, X13, #32

  (1134) 0x450c38 MOVZ	X0, #0

  (1134) 0x450c3c UBFM	X7, X3, #5, #63

  (1134) 0x450c40 ADD	X3, X1, #16

  (1134) 0x450c44 ADD	X27, X7, #1

  (1134) 0x450c48 ANDS	X25, X27, #4224

  (1134) 0x450c4c DUP	V31.2D, V31.D[0]

  (1134) 0x450c50 B.EQ	450d50

  (1134) 0x450c54 CMP	X25, #1

  (1134) 0x450c58 B.EQ	450d2c

  (1134) 0x450c5c CMP	X25, #2

  (1134) 0x450c60 B.EQ	450d10

  (1134) 0x450c64 CMP	X25, #3

  (1134) 0x450c68 B.EQ	450cf4

  (1134) 0x450c6c CMP	X25, #4

  (1134) 0x450c70 B.EQ	450cd8

  (1134) 0x450c74 CMP	X25, #5

  (1134) 0x450c78 B.EQ	450cbc

  (1134) 0x450c7c CMP	X25, #6

  (1134) 0x450c80 B.EQ	450ca0

  (1134) 0x450c84 LDR	Q3, [X4]

  (1134) 0x450c88 MOVZ	X0, #32

  (1134) 0x450c8c LDR	Q4, [X5]

  (1134) 0x450c90 FMUL	V0.2D, V3.2D, V31.2D

  (1134) 0x450c94 FMUL	V1.2D, V4.2D, V31.2D

  (1134) 0x450c98 STR	Q0, [X10, X26]

  (1134) 0x450c9c STR	Q1, [X1, #16]

  (1134) 0x450ca0 LDR	Q5, [X4, X0]

  (1134) 0x450ca4 LDR	Q2, [X5, X0]

  (1134) 0x450ca8 FMUL	V6.2D, V5.2D, V31.2D

  (1134) 0x450cac FMUL	V7.2D, V2.2D, V31.2D

  (1134) 0x450cb0 STR	Q6, [X1, X0]

  (1134) 0x450cb4 STR	Q7, [X3, X0]

  (1134) 0x450cb8 ADD	X0, X0, #32

  (1134) 0x450cbc LDR	Q29, [X4, X0]

  (1134) 0x450cc0 LDR	Q16, [X5, X0]

  (1134) 0x450cc4 FMUL	V17.2D, V29.2D, V31.2D

  (1134) 0x450cc8 FMUL	V18.2D, V16.2D, V31.2D

  (1134) 0x450ccc STR	Q17, [X1, X0]

  (1134) 0x450cd0 STR	Q18, [X3, X0]

  (1134) 0x450cd4 ADD	X0, X0, #32

  (1134) 0x450cd8 LDR	Q28, [X4, X0]

  (1134) 0x450cdc LDR	Q30, [X5, X0]

  (1134) 0x450ce0 FMUL	V19.2D, V28.2D, V31.2D

  (1134) 0x450ce4 FMUL	V20.2D, V30.2D, V31.2D

  (1134) 0x450ce8 STR	Q19, [X1, X0]

  (1134) 0x450cec STR	Q20, [X3, X0]

  (1134) 0x450cf0 ADD	X0, X0, #32

  (1134) 0x450cf4 LDR	Q26, [X4, X0]

  (1134) 0x450cf8 LDR	Q27, [X5, X0]

  (1134) 0x450cfc FMUL	V21.2D, V26.2D, V31.2D

  (1134) 0x450d00 FMUL	V22.2D, V27.2D, V31.2D

  (1134) 0x450d04 STR	Q21, [X1, X0]

  (1134) 0x450d08 STR	Q22, [X3, X0]

  (1134) 0x450d0c ADD	X0, X0, #32

  (1134) 0x450d10 LDR	Q24, [X4, X0]

  (1134) 0x450d14 LDR	Q25, [X5, X0]

  (1134) 0x450d18 FMUL	V23.2D, V24.2D, V31.2D

  (1134) 0x450d1c FMUL	V3.2D, V25.2D, V31.2D

  (1134) 0x450d20 STR	Q23, [X1, X0]

  (1134) 0x450d24 STR	Q3, [X3, X0]

  (1134) 0x450d28 ADD	X0, X0, #32

  (1134) 0x450d2c LDR	Q0, [X4, X0]

  (1134) 0x450d30 LDR	Q4, [X5, X0]

  (1134) 0x450d34 FMUL	V1.2D, V0.2D, V31.2D

  (1134) 0x450d38 FMUL	V5.2D, V4.2D, V31.2D

  (1134) 0x450d3c STR	Q1, [X1, X0]

  (1134) 0x450d40 STR	Q5, [X3, X0]

  (1134) 0x450d44 ADD	X0, X0, #32

  (1134) 0x450d48 CMP	X0, X13

  (1134) 0x450d4c B.EQ	450e38

    (1136) 0x450d50 LDR	Q2, [X4, X0]

    (1136) 0x450d54 ADD	X7, X0, #32

    (1136) 0x450d58 ADD	X28, X0, #64

    (1136) 0x450d5c ADD	X27, X0, #96

    (1136) 0x450d60 ADD	X26, X0, #128

    (1136) 0x450d64 LDR	Q6, [X5, X0]

    (1136) 0x450d68 ADD	X25, X0, #160

    (1136) 0x450d6c FMUL	V7.2D, V2.2D, V31.2D

    (1136) 0x450d70 FMUL	V29.2D, V6.2D, V31.2D

    (1136) 0x450d74 STR	Q7, [X1, X0]

    (1136) 0x450d78 STR	Q29, [X3, X0]

    (1136) 0x450d7c LDR	Q16, [X4, X7]

    (1136) 0x450d80 LDR	Q17, [X5, X7]

    (1136) 0x450d84 FMUL	V18.2D, V16.2D, V31.2D

    (1136) 0x450d88 FMUL	V28.2D, V17.2D, V31.2D

    (1136) 0x450d8c STR	Q18, [X1, X7]

    (1136) 0x450d90 STR	Q28, [X3, X7]

    (1136) 0x450d94 ADD	X7, X0, #192

    (1136) 0x450d98 LDR	Q30, [X4, X28]

    (1136) 0x450d9c LDR	Q19, [X5, X28]

    (1136) 0x450da0 FMUL	V20.2D, V30.2D, V31.2D

    (1136) 0x450da4 FMUL	V26.2D, V19.2D, V31.2D

    (1136) 0x450da8 STR	Q20, [X1, X28]

    (1136) 0x450dac STR	Q26, [X3, X28]

    (1136) 0x450db0 ADD	X28, X0, #224

    (1136) 0x450db4 ADD	X0, X0, #256

    (1136) 0x450db8 LDR	Q27, [X4, X27]

    (1136) 0x450dbc LDR	Q21, [X5, X27]

    (1136) 0x450dc0 FMUL	V22.2D, V27.2D, V31.2D

    (1136) 0x450dc4 FMUL	V24.2D, V21.2D, V31.2D

    (1136) 0x450dc8 STR	Q22, [X1, X27]

    (1136) 0x450dcc STR	Q24, [X3, X27]

    (1136) 0x450dd0 LDR	Q25, [X4, X26]

    (1136) 0x450dd4 LDR	Q23, [X5, X26]

    (1136) 0x450dd8 FMUL	V3.2D, V25.2D, V31.2D

    (1136) 0x450ddc FMUL	V0.2D, V23.2D, V31.2D

    (1136) 0x450de0 STR	Q3, [X1, X26]

    (1136) 0x450de4 STR	Q0, [X3, X26]

    (1136) 0x450de8 LDR	Q4, [X4, X25]

    (1136) 0x450dec LDR	Q1, [X5, X25]

    (1136) 0x450df0 FMUL	V5.2D, V4.2D, V31.2D

    (1136) 0x450df4 FMUL	V2.2D, V1.2D, V31.2D

    (1136) 0x450df8 STR	Q5, [X1, X25]

    (1136) 0x450dfc STR	Q2, [X3, X25]

    (1136) 0x450e00 LDR	Q6, [X4, X7]

    (1136) 0x450e04 LDR	Q7, [X5, X7]

    (1136) 0x450e08 FMUL	V29.2D, V6.2D, V31.2D

    (1136) 0x450e0c FMUL	V16.2D, V7.2D, V31.2D

    (1136) 0x450e10 STR	Q29, [X1, X7]

    (1136) 0x450e14 STR	Q16, [X3, X7]

    (1136) 0x450e18 LDR	Q17, [X4, X28]

    (1136) 0x450e1c LDR	Q18, [X5, X28]

    (1136) 0x450e20 FMUL	V28.2D, V17.2D, V31.2D

    (1136) 0x450e24 FMUL	V30.2D, V18.2D, V31.2D

    (1136) 0x450e28 STR	Q28, [X1, X28]

    (1136) 0x450e2c STR	Q30, [X3, X28]

    (1136) 0x450e30 CMP	X0, X13

    (1136) 0x450e34 B.NE	450d50

  (1134) 0x450e38 LDP	W26, W1, [SP, #100]

  (1134) 0x450e3c CBZ	W1, 450e7c

  (1134) 0x450e40 LDR	W0, [SP, #108]

  (1134) 0x450e44 ORR	W3, WZR, W26

  (1134) 0x450e48 LD1RD	{Z31.D}, P6/Z, [X8]

  (1134) 0x450e4c ADD	X2, X2, X3

  (1134) 0x450e50 ADD	X8, X12, X3

  (1134) 0x450e54 ADD	X27, X10, X2,LSL #3

  (1134) 0x450e58 CNTD	X7, ALL

  (1134) 0x450e5c ADD	X25, X9, X8,LSL #3

  (1134) 0x450e60 SUB	W26, W0, W26

  (1134) 0x450e64 WHILELO	P7.D, XZR, X26

  (1134) 0x450e68 LD1D	{Z19.D}, P7/Z, [X9, X8,LSL #3]

  (1134) 0x450e6c FMUL	Z20.D, Z19.D, Z31.D

  (1134) 0x450e70 ST1D	{Z20.D}, P7, [X27, MUL VL]

  (1134) 0x450e74 WHILELO	P0.D, X7, X26

  (1134) 0x450e78 B.NE	450eec

  (1134) 0x450e7c CMP	W11, W14

  (1134) 0x450e80 B.EQ	450e98

  (1134) 0x450e84 ADD	W6, W6, #1

  (1134) 0x450e88 CMP	W19, W6

  (1134) 0x450e8c B.LE	450eb4

  (1134) 0x450e90 ADD	W11, W11, #1

  (1134) 0x450e94 B	450bcc

(1132) 0x450e98 LDP	X25, X26, [SP, #64]

(1132) 0x450e9c LDP	X27, X28, [SP, #80]

(1132) 0x450ea0 LDP	X19, X20, [SP, #16]

(1132) 0x450ea4 LDP	X21, X22, [SP, #32]

(1132) 0x450ea8 LDP	X23, X24, [SP, #48]

(1132) 0x450eac LDP	X29, X30, [SP], #128

(1132) 0x450eb0 RET

  (1133) 0x450eb4 LDP	W8, W1, [SP, #116]

  (1133) 0x450eb8 MOVZ	W6, #0

  (1133) 0x450ebc ADD	W2, W1, #1

  (1133) 0x450ec0 SBFM	X15, X2, #0, #31

  (1133) 0x450ec4 STR	W2, [SP, #120]

  (1133) 0x450ec8 CMP	W8, W2

  (1133) 0x450ecc B.GT	450e90

(1132) 0x450ed0 LDR	W16, [SP, #124]

(1132) 0x450ed4 MOVZ	X15, #0

(1132) 0x450ed8 ADD	W11, W11, #1

(1132) 0x450edc ADD	W28, W16, #1

(1132) 0x450ee0 SBFM	X16, X28, #0, #31

(1132) 0x450ee4 STP	WZR, W28, [SP, #120]

(1132) 0x450ee8 B	450bcc

  (1134) 0x450eec LD1D	{Z26.D}, P0/Z, [X25, #1, MUL VL]

  (1134) 0x450ef0 FMUL	Z27.D, Z31.D, Z26.D

  (1134) 0x450ef4 ST1D	{Z27.D}, P0, [X27, #1, MUL VL]

  (1134) 0x450ef8 B	450e7c

  (1134) 0x450efc LDR	D21, [X9, X12,LSL #3]

  (1134) 0x450f00 ADD	X28, X3, X28

  (1134) 0x450f04 ORN	W3, WZR, W12

  (1134) 0x450f08 ADD	X1, X10, X28,LSL #3

  (1134) 0x450f0c ADD	X2, X12, #1

  (1134) 0x450f10 LDR	D22, [X7, X0]

  (1134) 0x450f14 LDR	W27, [SP, #112]

  (1134) 0x450f18 FMUL	D24, D21, D22

  (1134) 0x450f1c ADD	W26, W27, W3

  (1134) 0x450f20 AND	W25, W26, #128

  (1134) 0x450f24 STR	D24, [X1, X12,LSL #3]

  (1134) 0x450f28 CMP	W27, W2

  (1134) 0x450f2c B.LE	450e7c

  (1134) 0x450f30 CBZ	W25, 450ffc

  (1134) 0x450f34 CMP	W25, #1

  (1134) 0x450f38 B.EQ	450fdc

  (1134) 0x450f3c CMP	W25, #2

  (1134) 0x450f40 B.EQ	450fc8

  (1134) 0x450f44 CMP	W25, #3

  (1134) 0x450f48 B.EQ	450fb4

  (1134) 0x450f4c CMP	W25, #4

  (1134) 0x450f50 B.EQ	450fa0

  (1134) 0x450f54 CMP	W25, #5

  (1134) 0x450f58 B.EQ	450f8c

  (1134) 0x450f5c CMP	W25, #6

  (1134) 0x450f60 B.EQ	450f78

  (1134) 0x450f64 LDR	D25, [X9, X2,LSL #3]

  (1134) 0x450f68 LDR	D23, [X7, X0]

  (1134) 0x450f6c FMUL	D3, D25, D23

  (1134) 0x450f70 STR	D3, [X1, X2,LSL #3]

  (1134) 0x450f74 ADD	X2, X2, #1

  (1134) 0x450f78 LDR	D0, [X9, X2,LSL #3]

  (1134) 0x450f7c LDR	D4, [X7, X0]

  (1134) 0x450f80 FMUL	D1, D0, D4

  (1134) 0x450f84 STR	D1, [X1, X2,LSL #3]

  (1134) 0x450f88 ADD	X2, X2, #1

  (1134) 0x450f8c LDR	D5, [X9, X2,LSL #3]

  (1134) 0x450f90 LDR	D2, [X7, X0]

  (1134) 0x450f94 FMUL	D6, D5, D2

  (1134) 0x450f98 STR	D6, [X1, X2,LSL #3]

  (1134) 0x450f9c ADD	X2, X2, #1

  (1134) 0x450fa0 LDR	D7, [X9, X2,LSL #3]

  (1134) 0x450fa4 LDR	D29, [X7, X0]

  (1134) 0x450fa8 FMUL	D16, D7, D29

  (1134) 0x450fac STR	D16, [X1, X2,LSL #3]

  (1134) 0x450fb0 ADD	X2, X2, #1

  (1134) 0x450fb4 LDR	D17, [X9, X2,LSL #3]

  (1134) 0x450fb8 LDR	D18, [X7, X0]

  (1134) 0x450fbc FMUL	D28, D17, D18

  (1134) 0x450fc0 STR	D28, [X1, X2,LSL #3]

  (1134) 0x450fc4 ADD	X2, X2, #1

  (1134) 0x450fc8 LDR	D30, [X9, X2,LSL #3]

  (1134) 0x450fcc LDR	D31, [X7, X0]

  (1134) 0x450fd0 FMUL	D19, D30, D31

  (1134) 0x450fd4 STR	D19, [X1, X2,LSL #3]

  (1134) 0x450fd8 ADD	X2, X2, #1

  (1134) 0x450fdc LDR	D20, [X9, X2,LSL #3]

  (1134) 0x450fe0 LDR	D26, [X7, X0]

  (1134) 0x450fe4 LDR	W0, [SP, #112]

  (1134) 0x450fe8 FMUL	D27, D20, D26

  (1134) 0x450fec STR	D27, [X1, X2,LSL #3]

  (1134) 0x450ff0 ADD	X2, X2, #1

  (1134) 0x450ff4 CMP	W0, W2

  (1134) 0x450ff8 B.LE	450e7c

  (1134) 0x450ffc ORR	W28, WZR, W19

    (1135) 0x451000 LDR	D21, [X9, X2,LSL #3]

    (1135) 0x451004 ADD	X0, X2, #1

    (1135) 0x451008 ADD	X27, X2, #2

    (1135) 0x45100c ADD	X26, X2, #3

    (1135) 0x451010 ADD	X25, X2, #4

    (1135) 0x451014 LDR	D22, [X8]

    (1135) 0x451018 ADD	X19, X2, #5

    (1135) 0x45101c ADD	X7, X2, #6

    (1135) 0x451020 ADD	X3, X2, #7

    (1135) 0x451024 FMUL	D24, D21, D22

    (1135) 0x451028 STR	D24, [X1, X2,LSL #3]

    (1135) 0x45102c ADD	X2, X2, #8

    (1135) 0x451030 LDR	D25, [X9, X0,LSL #3]

    (1135) 0x451034 LDR	D23, [X8]

    (1135) 0x451038 FMUL	D3, D25, D23

    (1135) 0x45103c STR	D3, [X1, X0,LSL #3]

    (1135) 0x451040 LDR	D0, [X9, X27,LSL #3]

    (1135) 0x451044 LDR	D4, [X8]

    (1135) 0x451048 LDR	W0, [SP, #112]

    (1135) 0x45104c FMUL	D1, D0, D4

    (1135) 0x451050 STR	D1, [X1, X27,LSL #3]

    (1135) 0x451054 LDR	D5, [X9, X26,LSL #3]

    (1135) 0x451058 LDR	D2, [X8]

    (1135) 0x45105c FMUL	D6, D5, D2

    (1135) 0x451060 STR	D6, [X1, X26,LSL #3]

    (1135) 0x451064 LDR	D7, [X9, X25,LSL #3]

    (1135) 0x451068 LDR	D29, [X8]

    (1135) 0x45106c FMUL	D16, D7, D29

    (1135) 0x451070 STR	D16, [X1, X25,LSL #3]

    (1135) 0x451074 LDR	D17, [X9, X19,LSL #3]

    (1135) 0x451078 LDR	D18, [X8]

    (1135) 0x45107c FMUL	D28, D17, D18

    (1135) 0x451080 STR	D28, [X1, X19,LSL #3]

    (1135) 0x451084 LDR	D30, [X9, X7,LSL #3]

    (1135) 0x451088 LDR	D31, [X8]

    (1135) 0x45108c FMUL	D19, D30, D31

    (1135) 0x451090 STR	D19, [X1, X7,LSL #3]

    (1135) 0x451094 LDR	D20, [X9, X3,LSL #3]

    (1135) 0x451098 LDR	D26, [X8]

    (1135) 0x45109c FMUL	D27, D20, D26

    (1135) 0x4510a0 STR	D27, [X1, X3,LSL #3]

    (1135) 0x4510a4 CMP	W0, W2

    (1135) 0x4510a8 B.GT	451000

  (1134) 0x4510ac ORR	W19, WZR, W28

  (1134) 0x4510b0 B	450e7c

  (1134) 0x4510b4 MOVZ	W26, #0

  (1134) 0x4510b8 B	450e40

0x4510bc ADD	W14, W14, #1

0x4510c0 MOVZ	W5, #0

0x4510c4 B	450b18

0x4510c8 HINT	#0

0x4510cc HINT	#0

0x4510d0 HINT	#0

0x4510d4 HINT	#0

0x4510d8 HINT	#0

0x4510dc HINT	#0

0x46e728 HINT	#0

0x46e72c HINT	#0

0x46e730 HINT	#0

0x46e734 HINT	#0

0x46e738 HINT	#0

0x46e73c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1128-1131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h:156

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.50 to 12.50 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 37.50 to 18.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.50 to 1.00 cycles (37.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	8.33	8.33	8.33	6.00	6.00
cycles	4.50	4.50	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	8.33	8.33	8.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-37.50

Cycles summary

Front-end	9.75
Overall L1	15.00-37.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.50 cycles. At this rate:

2% of peak load performance is reached (2.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 450aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X23, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X23, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X23, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W3, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W4, W2, W3, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W20, W4, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403c90 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cc0 <@plt_start@+0x2d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W14, W20, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W5, W14, W21, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4510bc <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W14, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W14, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W9, W7, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
LDR W11, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W17, W10, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X23, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X20, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UDIV W15, W9, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
MSUB W6, W9, W19, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MSUB W1, W15, W11, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP W1, W15, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X12, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM W13, W24, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X26, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X16, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X27, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W2, W24, #1886	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W3, W24, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X13, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X23, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X4, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W2, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W3, W24, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450b18 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180
/home/hbollore/gnu/unknow_version/include/c++/14.0.1/bits/stl_vector.h:1128-1131
/home/hbollore/qaas-runs/171-275-7410/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h:156

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.50 to 1.00 cycles (37.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	8.33	8.33	8.33	6.00	6.00
cycles	4.50	4.50	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	8.33	8.33	8.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-37.50

Cycles summary

Front-end	9.75
Overall L1	15.00-37.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.50 cycles. At this rate:

2% of peak load performance is reached (2.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 450aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X23, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X23, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X23, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W3, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W19, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W4, W2, W3, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W20, W4, W19, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403c90 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403cc0 <@plt_start@+0x2d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W14, W20, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W5, W14, W21, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4510bc <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W14, W6, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W14, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W9, W7, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
LDR W11, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W17, W10, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X23, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X20, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UDIV W15, W9, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50
MSUB W6, W9, W19, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MSUB W1, W15, W11, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP W1, W15, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450ea0 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X12, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM W13, W24, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X26, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X16, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X27, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W28, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W2, W24, #1886	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W3, W24, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X13, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X23, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X4, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W2, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W3, W24, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450b18 <_ZN11qmcplusplus16BsplineAllocatorIdLm32ENS_10MallocatorIdLm32EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineAllocator >::setCoefficientsForOrbitals(int, int, Array&, multi_UBspline_3d_d*) [clone ._omp_fn.0]–	0.04	0.07
▼Loop 1132 - BsplineAllocator.hpp:171-180 - exec–	0	0
○Loop 1133 - BsplineAllocator.hpp:171-174 - exec	0	0
▼Loop 1134 - BsplineAllocator.hpp:179-180 - exec–	0	0
○Loop 1136 - BsplineAllocator.hpp:179-180 - exec	0.04	0.06
○Loop 1135 - BsplineAllocator.hpp:179-180 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code